A Hardware Efficient Multiple-Stream Pipeline FFT Processor for MIMO-OFDM Systems

[1]  Chu Yu,et al.  Area-Efficient 128- to 2048/1536-Point Pipeline FFT Processor for LTE and Mobile WiMAX Systems , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Shyh-Jye Jou,et al.  Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Shang-Ho Tsai,et al.  MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Song-Nien Tang,et al.  An Area- and Energy-Efficient Multimode FFT Processor for WPAN/WLAN/WMAN Systems , 2012, IEEE J. Solid State Circuits.

[5]  Dejan Markovic,et al.  Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example , 2012, IEEE Journal of Solid-State Circuits.

[6]  Yuan-Hao Huang,et al.  A variable-length FFT processor for 4×4 MIMO-OFDM systems , 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

[7]  P. Ampadu,et al.  An Area Efficient FFT/IFFT Processor for MIMO-OFDM WLAN 802.11n , 2009, J. Signal Process. Syst..

[8]  Chen-Yi Lee,et al.  Design of an FFT/IFFT Processor for MIMO OFDM Systems , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  In-Cheol Park,et al.  Balanced Binary-Tree Decomposition for Area-Efficient Pipelined FFT Processing , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Chen-Yi Lee,et al.  A 1-GS/s FFT/IFFT processor for UWB applications , 2005, IEEE J. Solid State Circuits.

[11]  Jesús Grajal,et al.  Pipelined Radix-$2^{k}$ Feedforward FFT Architectures , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  E.E. Swartzlander,et al.  A radix 4 delay commutator for fast Fourier transform processor implementation , 1984, IEEE Journal of Solid-State Circuits.