Using Existing Reconfigurable Logic in 3D Die Stacks for Test

We propose an architecture for an FPGA-based tester for a 3D stacked IC. Our design exploits the underlying structure of the FPGA, allowing it to be used to efficiently store and apply predefined test patterns at a high bandwidth, reducing the FPGA resources required and often reducing scan shift toggling. The proposed approach and its advantages can generally also be applied to 2.5D multi-die circuits containing FPGAs.

[1]  Theodore W. Manikas,et al.  Repairing a 3-D Die-Stack Using Available Programmable Logic , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Raimund Ubar,et al.  Fast extended test access via JTAG and FPGAs , 2009, 2009 International Test Conference.

[3]  Nilanjan Mukherjee,et al.  Embedded deterministic test , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Jun Zhou,et al.  BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  K. Saban.  Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity , Bandwidth , and Power Efficiency , 2009 .

[6]  Sergei Devadze,et al.  Virtual reconfigurable scan-chains on FPGAs for optimized board test , 2015, 2015 16th Latin-American Test Symposium (LATS).

[7]  Vivek Chickermane,et al.  DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks , 2012, 2012 IEEE International Test Conference.

[8]  Bruno Rouzeyre,et al.  A JTAG based 3D DfT architecture using automatic die detection , 2013, Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).

[9]  Payel Ghosh,et al.  Session Based Core Test Scheduling for 3D SOCs , 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

[10]  Ajay Khoche,et al.  FPGA-Based Embedded Tester with a P1687 Command, Control, and Observe-System , 2013, IEEE Design & Test.

[11]  Matteo Sonza Reorda,et al.  An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs , 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

[12]  Walter Stechele,et al.  Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems , 2010, ARC.

[13]  Xi Shen,et al.  Built-in Self-Repair in a 3D die stack using programmable logic , 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

[14]  Xiaoxia Wu,et al.  Scan-chain design and optimization for three-dimensional integrated circuits , 2009, JETC.

[15]  John Park.  Thinking outside of the chip , 2010, ISPD '10.

[16]  R. Chaware,et al.  Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[17]  Krishnendu Chakrabarty,et al.  Test-cost optimization and test-flow selection for 3D-stacked ICs , 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).