Energy efficient parameterized FFT architecture

In this paper, we revisit the classic Fast Fourier Transform (FFT) for energy efficient designs on FPGAs. A parameterized FFT architecture is proposed to identify the design trade-offs in achieving energy efficiency. We first perform design space exploration by varying the algorithm mapping parameters, such as the degree of vertical and horizontal parallelism, that characterize decomposition based FFT algorithms. Then we explore an energy efficient design by empirical selection on the values of the chosen architecture parameters, including the type of memory elements, the type of interconnection network and the number of pipeline stages. The trade offs between energy, area, and time are analyzed using two performance metrics: the energy efficiency (defined as the number of operations per Joule) and the Energy×Area×Time (EAT) composite metric. From the experimental results, a design space is generated to demonstrate the effect of these parameters on the various performance metrics. For N-point FFT (16 ≤ N ≤ 1024), our designs achieve up to 28% and 38% improvement in the energy efficiency and EAT, respectively, compared with a state-of-the-art design.

[1]  Bevan M. Baas,et al.  A low-power, high-performance, 1024-point FFT processor , 1999, IEEE J. Solid State Circuits.

[2]  Mats Torkelson,et al.  A new approach to pipeline FFT processor , 1996, Proceedings of International Conference on Parallel Processing.

[3]  C. K. Yuen,et al.  Theory and Application of Digital Signal Processing , 1978, IEEE Transactions on Systems, Man, and Cybernetics.

[4]  A. Lynn Abbott,et al.  Implementation of a 2-D Fast Fourier Transform on an FPGA-Based Custom Computing Machine , 1995, FPL.

[5]  James C. Hoe,et al.  Automatic generation of customized discrete Fourier transform IPs , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[6]  Ray C. C. Cheung,et al.  Low complexity and hardware-friendly spectral modular multiplication , 2012, 2012 International Conference on Field-Programmable Technology.

[7]  Viktor K. Prasanna,et al.  Energy-efficient signal processing using FPGAs , 2003, FPGA '03.

[8]  H. Noda,et al.  A high-performance and energy-efficient FFT implementation on super parallel processor (MX) for mobile multimedia applications , 2009, 2008 International Symposium on Intelligent Signal Processing and Communications Systems.

[9]  James C. Hoe,et al.  Permuting streaming data using RAMs , 2009, JACM.

[10]  H. Kimura,et al.  Numerical Analysis of Dynamic SNR Management by Controlling DSP Calculation Precision for Energy-Efficient OFDM-PON , 2012, IEEE Photonics Technology Letters.

[11]  Alvin M. Despain,et al.  Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations , 1984, IEEE Transactions on Computers.

[12]  James C. Hoe,et al.  Fast and accurate resource estimation of automatically generated custom DFT IP cores , 2006, FPGA '06.

[13]  Arvind Sudarsanam,et al.  High level-application analysis techniques & architectures - to explore design possibilities for reduced reconfiguration area overheads in FPGAs executing compute intensive applications , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[14]  E. V. Jones,et al.  A pipelined FFT processor for word-sequential data , 1989, IEEE Trans. Acoust. Speech Signal Process..

[15]  Chein-Wei Jen,et al.  High-speed and low-power split-radix FFT , 2003, IEEE Trans. Signal Process..