An anti-harmonic MDLL for phase-aligned on-chip clock multiplication
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[1] Tad A. Kwasniewski,et al. A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.
[2] Shen-Iuan Liu,et al. An All-Digital Fast-Locking Programmable DLL-Based Clock Generator , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.
[3] B.M. Helal,et al. A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance , 2008, IEEE Journal of Solid-State Circuits.
[5] Amr Elshazly,et al. Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops , 2013, IEEE Journal of Solid-State Circuits.
[6] Sheng Ye,et al. A multiple-crystal interface PLL with VCO realignment to reduce phase noise , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[7] Giovanni Marucci,et al. 21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
[8] Ron Ho,et al. A 4.6GHz MDLL with −46dBc reference spur and aperture position tuning , 2011, 2011 IEEE International Solid-State Circuits Conference.
[9] William J. Dally,et al. A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips , 2002, IEEE J. Solid State Circuits.
[10] Jongsun Kim,et al. A 2-4 GHz fast-locking frequency multiplying delay-locked loop , 2017, IEICE Electron. Express.