Jongsun Kim

发表

Manufacturing Process for Bush Type Bearing Metal Using Centrifugal Casting

Won-Sik Choi, Mi Jung Sin, Sun Mi Choi, 2014 .

An anti-harmonic MDLL for phase-aligned on-chip clock multiplication

Jongsun Kim, B. H. Bae, 2018, IEICE Electron. Express.

5 GHz all-digital delay-locked loop for future memory systems beyond double data rate 4 synchronous dynamic random access memory

Jongsun Kim, Dongyeol Lee, Dongyeol Lee, 2015 .

An Area-Efficient Anti-Harmonic Programmable MDLL-Based Frequency Multiplier

Jongsun Kim, Geontae Park, Sungken Lee, 2012 .

Effective representation using ICA for face recognition robust to local distortion and partial occlusion

Jongsun Kim, Juneho Yi, Jongmoo Choi, 2005, IEEE Transactions on Pattern Analysis and Machine Intelligence.

A low power capacitive coupled bus interface based on pulsed signaling

Jongsun Kim, Ingrid Verbauwhede, Jung-Hwan Choi, 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

A High-Resolution Dual-Loop Digital DLL

Jongsun Kim, Sangwoo Han, Sangwoo Han, 2016 .

A Simple Phase Interpolator based Spread Spectrum Clock Generator Technique

Jongsun Kim, Jae-Hee You, Kyoung-Rok Lee, 2010 .

A low-power fast-lock DCC with a digital duty-cycle adjuster for LPDDR3 and LPDDR4 DRAMs

Jongsun Kim, S. W. Han, Jongsun Kim, 2018, IEICE Electronics Express.

A 7-GHz Fast-Lock 2-Step TDC-based All-Digital DLL for Post-DDR4 SDRAMs

Jongsun Kim, Dongjun Park, Jongsun Kim, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

A Low-Overhead and Low-Power RF Transceiver for Short-Distance On- and Off-Chip Interconnects

Jongsun Kim, Gyungsu Byun, M. Frank Chang, 2011, IEICE Trans. Electron..

Fully-differential self-biased bio-potential amplifier

Jongsun Kim, Wentai Liu, M. Chae, 2008 .

A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs

Jongsun Kim, Seo Weon Heo, Junsub Yoon, 2017, IEICE Electron. Express.

An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling

Jongsun Kim, Mau-Chung Frank Chang, Yanghyo Kim, 2012, IEEE Journal of Solid-State Circuits.

A MDLL-based multi-phase clock multiplier

Jongsun Kim, Junsub Yoon, 2016, 2016 International SoC Design Conference (ISOCC).

202pJ/bit area-efficient ASK demodulator for high-density visual prostheses

Jongsun Kim, Kenneth D. Pedrotti, 2012 .

Double edge trailing PWM based full digital audio amplifier design

Jongsun Kim, Seo Weon Heo, 2012, 2012 IEEE International Conference on Consumer Electronics (ICCE).

Robust Face Recognition Based on Part-Based Localized Basis Images

Jongsun Kim, Juneho Yi, 2005, ICIAP.

An All-digital Delay-locked Loop using a Lock-in Pre-search Algorithm for High-speed DRAMs

Jongsun Kim, Jongsun Kim, 2017 .

Robust Skin Color Segmentation Using a 2D Plane of RGB Color Space

Jongsun Kim, Juneho Yi, Jongmoo Choi, 2003, ISCIS.

A low-power SerDes for high-speed on-chip networks

Jongsun Kim, Dongjun Park, Junsub Yoon, 2017, 2017 International SoC Design Conference (ISOCC).

Area-efficient digitally controlled CMOS feedback delay element with programmable duty cycle

Jongsun Kim, Jongsun Kim, 2009, IEICE Electron. Express.

An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling

Jason Cong, Jongsun Kim, Mau-Chung Frank Chang, 2011, 2011 IEEE International Solid-State Circuits Conference.

A 10 Gbps SerDes for wireless chip-to-chip communication

Jongsun Kim, Jintae Kim, Sangwoo Han, 2015, 2015 International SoC Design Conference (ISOCC).

Design of clock duty-cycle correction circuits for high-speed SoCs

Jongsun Kim, Sangwoo Han, 2013 .

A high-resolution wide-range dual-loop digital delay-locked loop using a hybrid search algorithm

Jongsun Kim, Sangwoo Han, Sangwoo Han, 2012, 2012 IEEE Asian Solid State Circuits Conference (A-SSCC).

A Low-Power Single Chip Li-Ion Battery Protection IC

Jongsun Kim, Seunghyeong Lee, Yongjae Jeong, 2015 .

A fast-locking clock multiplying DLL

Jongsun Kim, Bongho Bae, 2016, 2016 International SoC Design Conference (ISOCC).

Hybrid duty-cycle corrector circuit with dual feedback loop

Jongsun Kim, Sangwoo Han, Sangwoo Han, 2011 .

Reconfigurable memory bus systems using multi-Gbps/pin CDMA I/O transceivers

Zhiwei Xu, Jongsun Kim, Mau-Chung Frank Chang, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

A Fast-Locking All-Digital Multiplying DLL for Fractional-Ratio Dynamic Frequency Scaling

Jongsun Kim, Sangwoo Han, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Changeable Biometric System That Uses Parts-Based Localized Representation for Face Recognition

Jongsun Kim, Chulhan Lee, Jaihie Kim, 2007, 2007 IEEE Workshop on Automatic Identification Advanced Technologies.

A Low-power 3.52 Gbps SerDes with a MDLL Frequency Multiplier for High-speed On-chip Networks

Jongsun Kim, Hyungsik Shin, 2018 .

An anti-boundary switching fine-resolution digital delay-locked loop

Jongsun Kim, Jongsun Kim, 2018 .

A single chip Li-Ion battery protection IC with low standby mode auto release

Jongsun Kim, Seunghyeong Lee, Yongjae Jeong, 2014, 2014 International SoC Design Conference (ISOCC).

An RF/baseband FDMA-interconnect transceiver for reconfigurable multiple access chip-to-chip communication

Zhiwei Xu, Jongsun Kim, Qun Gu, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

A CMOS Duty Cycle Corrector Using Dynamic Frequency Scaling for Coarse and Fine Tuning Adjustment

Jongsun Kim, Sangwoo Han, 2012 .

Study on High Efficiency EEFL Backlight inverter for 32-inch LCD TV

Jongsun Kim, Gun-Woo Moon, Won-Sik Oh, 2005 .

ICA Based Face Recognition Robust to Partial Occlusions and Local Distortions

Jongsun Kim, Juneho Yi, Jongmoo Choi, 2004, ICBA.

A 30 Gb/s All-Digital CDR with a Phase Error Compensator

Jongsun Kim, Heejae Hwang, Kunhoo Park, 2020, 2020 International Conference on Electronics, Information, and Communication (ICEIC).

A Reset-Free Anti-Harmonic Programmable MDLL- Based Frequency Multiplier

Jongsun Kim, Hyungtak Kim, Geontae Park, 2013 .

A 0.1–1.5 GHz all-digital phase inversion delay-locked loop

Taejin Kim, Jongsun Kim, Sangwoo Han, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A low-power wideband multi-frequency synthesizer for mobile TV tuner ICs

Jongsun Kim, Hojung Ju, 2010, IEICE Electron. Express.

Wireline/wireless RF-Interconnect for future SoC

Jongsun Kim, Gyungsu Byun, Sai-Wang Tam, 2011, 2011 IEEE International Symposium on Radio-Frequency Integration Technology.

Three-dimensional circuit integration based on self-synchronized RF-interconnect using capacitive coupling

Zhiwei Xu, Jongsun Kim, Qun Gu, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems

Jongsun Kim, Mau-Chung Frank Chang, Ingrid Verbauwhede, 2008, IEEE Transactions on Computers.

Face Recognition Based on ICA Combined with FLD

Jongsun Kim, Juneho Yi, Jongmoo Choi, 2002, Biometric Authentication.

Changeable Face Representations Suitable for Human Recognition

Jongsun Kim, Chulhan Lee, Jeung-Yoon Choi, 2007, ICB.

A 2-4 GHz fast-locking frequency multiplying delay-locked loop

Jongsun Kim, Bongho Bae, 2017, IEICE Electron. Express.

A programmable delay-locked loop based clock multiplier

Jongsun Kim, Hyungtak Kim, Geontae Park, 2012, 2012 International SoC Design Conference (ISOCC).

Wireline and wireless RF-Interconnect for next generation SoC systems

Jongsun Kim, Sai-Wang Tam, M. Frank Chang, 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

A Study on Improving the Tractor ROPS and Seatbelt use of Korean Farmers

Jongsun Kim, Sun Choi, Jin-Oh Kim, 2010 .

Face Recognition Based on Locally Salient ICA Information

Jongsun Kim, Juneho Yi, Jongmoo Choi, 2004, ECCV Workshop BioAW.

An Area-Efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier

Jongsun Kim, Sangwoo Han, Jongtae Lim, 2016 .

Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication

Jongsun Kim, Mau-Chung Frank Chang, Ingrid Verbauwhede, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 2.7 Gb/s CDMA-interconnect transceiver chip set with multi-level signal data recovery for re-configurable VLSI systems

Zhiwei Xu, Jongsun Kim, Hyunchol Shin, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

A 0.15 to 2.2 GHz all-digital delay-locked loop

Jongsun Kim, Geontae Park, Dongjun Park, 2017, 2017 15th IEEE International New Circuits and Systems Conference (NEWCAS).