FEKIS: a fast architecture-level thermal analyzer for online thermal regulation

Owning to increasing power consumption and the corresponding heat dissipated on die, efficient on-chip temperature regulation becomes imperative for today's high performance microprocessors. Temperature tracking based on the on-chip thermal sensors is not sufficient as the temperature hot spots keep changing with the load. One way to mitigate this problem is by means of software sensors, where temperature of any location is computed based on realtime power information and calibrated with the physical sensors. In this paper, we present a very efficient numerical thermal analyzer, which is suitable for fast temperature tracking and online thermal regulation. The proposed method, called FEKIS, combines two existing numerical techniques: extended Krylov subspace reduction technique to reduce the thermal circuit complexity and large-step integration method to exploits the piecewise constant power input traces, which is typical in the power traces at the architecture level. Experimental results show that FEKIS runs 10X faster than the precise time-step integration method only and $1000X$ faster than the traditional numerical integration method with high accuracy.

[1]  YangJun,et al.  Efficient power modeling and software thermal sensing for runtime temperature monitoring , 2008 .

[2]  Kevin Skadron,et al.  Compact thermal modeling for temperature-aware design , 2004, Proceedings. 41st Design Automation Conference, 2004..

[3]  Brad Calder,et al.  Basic block distribution analysis to find periodic behavior and simulation points in applications , 2001, Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques.

[4]  Kevin Skadron,et al.  Temperature-Aware Microarchitecture: Extended Discussion and Results , 2003 .

[5]  Margaret Martonosi,et al.  Dynamic thermal management for high-performance microprocessors , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[6]  Kevin Skadron,et al.  Temperature-aware microarchitecture , 2003, ISCA '03.

[7]  Kevin Skadron,et al.  A Case for Thermal-Aware Floorplanning at the Microarchitectural Level , 2005, J. Instr. Level Parallelism.

[8]  Wei Wu,et al.  Efficient power modeling and software thermal sensing for runtime temperature monitoring , 2007, TODE.

[9]  Kevin Skadron,et al.  Using performance counters for runtime temperature sensing in high-performance processors , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[10]  Sheldon X.-D. Tan,et al.  Advanced Model Order Reduction Techniques in VLSI Design , 2007 .

[11]  Wanxie Zhong,et al.  On a New Time Integration Method for Solving Time Dependent Partial Differential Equations , 1996 .

[12]  Janet Roveda,et al.  Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources , 2000, Proceedings 37th Design Automation Conference.

[13]  Krishnendu Chakrabarty,et al.  Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Wei Wu,et al.  Efficient thermal simulation for run-time temperature tracking and management , 2005, 2005 International Conference on Computer Design.

[15]  Dhiraj K. Pradhan,et al.  Thermal-aware testing of network-on-chip using multiple-frequency clocking , 2006, 24th IEEE VLSI Test Symposium.

[16]  Mircea R. Stan,et al.  System level leakage reduction considering the interdependence of temperature and leakage , 2004, Proceedings. 41st Design Automation Conference, 2004..

[17]  Stephen H. Gunther,et al.  Managing the Impact of Increasing Microprocessor Power Consumption , 2001 .