Correct Hardware Design and Verification Methods

The current state of hardware logic design and verification is discussed based on the project flow used for IBM’s Power4 and Power5 projects. The frequency and power requirements for these high-end chips constrain the logic design to a detailed RT-level in order to control physical effects. On the other hand, the complexity of the designs which embrace many speculative mechanisms to push functional performance to higher levels force an early specification of the microarchitecture with a high-level model. A review how high-level modeling has advanced is based on the discussion which mechanisms of abstraction raise the specification above the RTlevel. A critique of specification language design leads to the appeal to the formal verification community to focus efforts on the front-end of the high-level design process to help shape modeling languages with formally defined semantics that avoid the mistakes made in the past with ad-hoc language designs. D. Geist and E. Tronci (Eds.): CHARME 2003, LNCS 2860, p. 1, 2003. c © Springer-Verlag Berlin Heidelberg 2003 The Charme of Abstract Entities