Eecient Vlsi Implementation of Iterative Solutions to Sparse Linear Systems

We propose a novel way of solving systems of linear equations with sparse coe cient matrices using iterative methods on a VLSI array. The nonzero entries of the coe cient matrix are mapped onto a processor array of size pe pe, where e is the number of nonzero elements, n is the number of equations and e n. The data transport problem that arises because of this mapping is solved using an e cient routing technique. Preprocessing is carried out on the iteration matrix of the system to compute the routing control-words that are used in the data transfer. This results in O(pe) time for each iteration of the method, with a small constant factor. As compared to existing VLSI methods for solving the problem, the proposed method yields a superior time performance, greater ease of programmability and an area e cient design. We also develop a second implementation of our algorithm that uses a slightly higher number of communication steps, but reduces the number of arithmetic operations to O(log e). The latter algorithm is suitable for many other architectures as well. The algorithm can be implemented in O(log e) time using e processors on a hypercube, shu e-exchange, and cubeconnected-cycles. 1