Fault testing is a crucially important issue in the development of VLSI circuits. Although fault testing problems have been studied extensively for digital systems, especially in the context of classical faults in logic circuits, most of the work deals exclusively with the problem of finding an efficient algorithm for generating test. Very little effort has been devoted to revealing the underline fundamental structure of testing problem. As a result, the techniques and theories developed in digital system testing have not been successfully extended to more general cases. On the other hand, the demand is mounting for techniques and theories of fault testing not only for digital systems, but also for analog/digital hybrid systems. Therefore, a unified theory for fault testing is needed.
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