High Performance Computing — HiPC 2001

In this paper, we investigate and analyze the stability properties of heterogeneous networks, which use a combination of different universally stable queueing policies for packet routing, in the Adversarial Queueing model. We interestingly prove that the combination of SIS and LIS policies, LIS and NTS policies, and LIS and FTG policies leads to instability for specific networks and injection rates that are presented. It is also proved that the combination of SIS and FTG policies, SIS and NTS policies, and FTG and NTS policies is universally stable. Furthermore, we prove that FIFO is non-stable for any r ≥ 0.749, improving significantly the previous best known bounds of [2,10], by using new techniques for adversary construction and tight analysis of the packet flow time evolution. We also show a graph for which FIFO is stable for any adversary with injection rate r ≤ 0.1428, and, by generalizing, we present upper bounds for stability of any network under the FIFO protocol, answering partially an open question raised by Andrews et al. in [2]. The work presented here combines new and recent results of the authors.

[1]  Bantwal R. Rau Dynamically scheduled VLIW processors , 1993, MICRO 1993.

[2]  Andrew Wolfe,et al.  A variable instruction stream extension to the VLIW architecture , 1991, ASPLOS IV.

[3]  Dean M. Tullsen,et al.  Simultaneous multithreading: Maximizing on-chip parallelism , 1995, Proceedings 22nd Annual International Symposium on Computer Architecture.

[4]  Andrew R. Pleszkun,et al.  Implementing Precise Interrupts in Pipelined Processors , 1988, IEEE Trans. Computers.

[5]  Thomas M. Conte,et al.  Treegion scheduling for wide issue processors , 1998, Proceedings 1998 Fourth International Symposium on High-Performance Computer Architecture.

[6]  Andrew R. Pleszkun,et al.  Implementation of precise interrupts in pipelined processors , 1985, ISCA '98.

[7]  William J. Dally,et al.  Processor coupling: integrating compile time and runtime scheduling for parallelism , 1992, ISCA '92.

[8]  William J. Dally,et al.  Concurrent Event Handling through Multithreading , 1999, IEEE Trans. Computers.

[9]  Trevor N. Mudge,et al.  Design Tradeoffs For Software-managed Tlbs , 1994, Proceedings of the 20th Annual International Symposium on Computer Architecture.

[10]  Kenneth C. Yeager The Mips R10000 superscalar microprocessor , 1996, IEEE Micro.

[11]  Haitham Akkary,et al.  A dynamic multithreading processor , 1998, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture.

[12]  Hwa C. Torng,et al.  Interrupt Handling for Out-of-Order Execution Processors , 1993, IEEE Trans. Computers.

[13]  Chuan-lin Wu,et al.  A Benchmark Evaluation of a Multi-threaded RISC Processor Architecture , 1991, ICPP.

[14]  William A. Havanki,et al.  Treegion Scheduling for Vliw Processors , 1997 .

[15]  Gurindar S. Sohi,et al.  Instruction issue logic for high-performance, interruptable pipelined processors , 1987, ISCA '87.

[16]  Harvey G. Cragon,et al.  Interrupt Processing in Concurrent Processors , 1995, Computer.

[17]  Anoop Gupta,et al.  The impact of architectural trends on operating system performance , 1995, SOSP.

[18]  M. Dubois,et al.  Tolerating late memory traps in ILP processors , 1999, Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367).

[19]  Gurindar S. Sohi,et al.  The Expandable Split Window Paradigm for Exploiting Fine-grain Parallelism , 1992, [1992] Proceedings the 19th Annual International Symposium on Computer Architecture.