Towards Green Routers: Depth-Bounded Multi-Pipeline Architecture for Power-Efficient IP Lookup

Power consumption has become a major concern in designing IP lookup engines for next generation routers. Although TCAMs dominate today's high-end routers, they are not scalable in terms of clock rate and power consumption. SRAM-based pipeline solutions are considered promising alternatives for high-speed IP lookup engines. However, existing SRAM-based pipeline architectures suffer from high power consumption in the worst cases, due to the large memory size and the long pipeline depth. This paper proposes a power-efficient SRAM-based pipelined IP lookup engine for future "green" routers. Both chip-level parallelism and clock gating techniques are employed to reduce the power consumption. With the aid of small TCAMs, a two-phase scheme is proposed to partition a routing trie into a number of height-bounded subtries, which are then mapped onto multiple pipelines. Each IP lookup is completed through a bounded number of accesses on small size memories. Simulation experiments using real-life traces show that our solution can store a backbone routing table with over 200 K prefixes in 4.25 MB memory, sustains a throughput of 400 Gbps, and achieves up to 7-fold and 3-fold reductions in power consumption over the state-of-the-art TCAM-based and SRAM-based solutions, respectively.