Algorithmic Techniques for Memory Energy Reduction

Energy dissipation is a critical concern for battery-powered embedded systems. Memory energy contributes significantly to overall energy in data intensive applications. Low power memory systems are being designed that support multiple power states of memory banks. In low power states, energy dissipation is reduced but time to access memory is increased.We abstract an energy model for the memory system and exploit it to develop algorithmic techniques for memory energy reduction. This is achieved by exploring the structure and data access pattern of a given algorithm to devise memory power management schedules. We illustrate our approach through two well-known embedded benchmarks - Matrix Multiplication and Fast Fourier Transform. The optimality of our schemes is discussed using information theoretic lower bounds on memory energy. Simulations demonstrate that significant energy reduction can be achieved by using our approach over state-of-the-art implementations.

[1]  Thomas Alexander,et al.  Distributed prefetch-buffer/cache design for high performance memory systems , 1996, Proceedings. Second International Symposium on High-Performance Computer Architecture.

[2]  Francky Catthoor,et al.  Random-access data storage components in customized architectures , 2001, IEEE Design & Test of Computers.

[3]  Diederik Verkest,et al.  System-level interconnect architecture exploration for custom memory organizations , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

[4]  Niraj K. Jha,et al.  Static and dynamic variable voltage scheduling algorithms for real-time heterogeneous distributed embedded systems , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[5]  Rajesh Gupta,et al.  Architectural adaptation for power and performance , 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).

[6]  H. T. Kung,et al.  I/O complexity: The red-blue pebble game , 1981, STOC '81.

[7]  Luca Benini,et al.  Layout-driven memory synthesis for embedded systems-on-chip , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Nikil D. Dutt,et al.  Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors , 2001, IEEE Des. Test Comput..

[9]  Todd M. Austin,et al.  The SimpleScalar tool set, version 2.0 , 1997, CARN.

[10]  Krishna V. Palem,et al.  Power Optimization of Embedded Memory Systems via Data Remapping , 2002 .

[11]  Viktor K. Prasanna,et al.  Cache conscious Walsh-Hadamard transform , 2001, 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221).

[12]  Majid Sarrafzadeh,et al.  Memory Segmentation to Exploit Sleep Mode Operation , 1995, 32nd Design Automation Conference.

[13]  Chaitali Chakrabarti,et al.  Memory exploration for low power, embedded systems , 1999, DAC '99.

[14]  Mahmut T. Kandemir,et al.  Influence of array allocation mechanisms on memory system energy , 2001, Proceedings 15th International Parallel and Distributed Processing Symposium. IPDPS 2001.

[15]  Sandeep Sen,et al.  Towards a theory of cache-efficient algorithms , 2000, SODA '00.

[16]  Anantha Chandrakasan,et al.  JouleTrack: a web based tool for software energy profiling , 2001, DAC '01.

[17]  Mary Jane Irwin,et al.  Architecture-level power estimation and design experiments , 2001, TODE.

[18]  Erik Brockmeyer,et al.  Data Memory Organization and Optimizations in Application-Specific Systems , 2001, IEEE Des. Test Comput..

[19]  Alvin R. Lebeck,et al.  Power aware page allocation , 2000, SIGP.

[20]  Johan Pouwelse,et al.  Dynamic voltage scaling on a low-power microprocessor , 2001, MobiCom '01.

[21]  Carla Schlatter Ellis,et al.  Memory controller policies for DRAM power management , 2001, ISLPED '01.

[22]  Helmut Prodinger,et al.  On the Balance Property of Patricia Tries: External Path Length Viewpoint , 1989, Theor. Comput. Sci..

[23]  Nikil Dutt.  Memory Organization and Exploration for Embedded Systems-on-Silicon , 1997 .