Improving post-silicon error detection with topological selection of trace signals

Drastic growth in design complexity of VLSI circuits has increased the chances of bugs escaping to first released silicon. This has resulted in an increased emphasis on post-silicon validation and debug which is typically hindered by limited observability of internal signals. Trace buffers assist in curbing this bottleneck by storing selected signal states for limited clock cycles. For efficient use of these on-chip buffers, devising a proper selection criterion is of utmost importance. Maximization of restoration of untraced signals is a widely utilized signal selection metric. However, this approach has been seen to not be very effective for error detection. This paper proposes a trace signal selection technique based on error transmission, taking into account the topology of the design. The proposed signal selection methodology can be effectively applied to trace as well as a combination of trace and scan based observability techniques. Experimental evaluation of the proposed methodology on different design errors indicates improvement in error detection as compared to restorability based selection techniques.