A novel asymmetrical SRAM cell tolerant to soft errors

In this paper, we propose a novel asymmetrical 11T SRAM cell design that has fault correction capability. In addition, the Layout design through Error-Aware transistor Positioning (LEAP) technique is adopted in designing the layout of this proposed 11T cell. The area of the proposed 11T cell without using LEAP technique (regular 11T) is 76% larger than that of traditional 6T cell and 16% larger than that of the Quatro cell. The area of 11T cell with LEAP technique (LEAP-11T) is 15% larger than that of regular 11T cell and 103% larger than that of 6T cell. Simulation results show that the error cross section of regular 11T is 17X lower and 2.8X lower than that of traditional 6T at LET = 10 and 30 MeV-cm2/mg respectively in normal strikes; and it is 2.2X lower than Quatro cell when LET = 30 MeV-cm2/mg in normal strikes. With LEAP technique implemented, the LEAP-11T cell's error cross section is 6.5X lower than the Quatro cell when LET = 10 MeV-cm2/mg in angled strikes.

[1]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[2]  S. Jahinuzzaman,et al.  A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability , 2009, IEEE Transactions on Nuclear Science.

[3]  R. Wong,et al.  Single-Event Tolerant Flip-Flop Design in 40-nm Bulk CMOS Technology , 2011, IEEE Transactions on Nuclear Science.

[4]  I. Linscott,et al.  Design Framework for Soft-Error-Resilient Sequential Cells , 2011, IEEE Transactions on Nuclear Science.

[5]  R. Koga.  Single-event effect ground test issues , 1996 .

[6]  Jing Guo,et al.  Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  R. Reed,et al.  Mitigation Techniques for Single-Event-Induced Charge Sharing in a 90-nm Bulk CMOS Process , 2009, IEEE Transactions on Device and Materials Reliability.

[8]  Dhiraj K. Pradhan,et al.  Design Metrics of SRAM Bitcell , 2013 .

[9]  R. Wong,et al.  Single-Event Performance and Layout Optimization of Flip-Flops in a 28-nm Bulk Technology , 2013, IEEE Transactions on Nuclear Science.

[10]  Ivan R. Linscott,et al.  LEAP: Layout Design through Error-Aware Transistor Positioning for soft-error resilient sequential cell design , 2010, 2010 IEEE International Reliability Physics Symposium.

[11]  J. Draper,et al.  The DF-dice storage element for immunity to soft errors , 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

[12]  B.L. Bhuva,et al.  Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process , 2008, 2008 IEEE International Reliability Physics Symposium.

[13]  Riadul Islam,et al.  TSPC-DICE: A single phase clock high performance SEU hardened flip-flop , 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

[14]  Shi-Jie Wen,et al.  Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS , 2012, IEEE Trans. Circuits Syst. I Regul. Pap..

[15]  L.W. Massengill,et al.  Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design , 2005, IEEE Transactions on Nuclear Science.

[16]  Fabrizio Lombardi,et al.  Design of a Nanometric CMOS Memory Cell for Hardening to a Single Event With a Multiple-Node Upset , 2014, IEEE Transactions on Device and Materials Reliability.

[17]  Lloyd W. Massengill,et al.  Basic mechanisms and modeling of single-event upset in digital microelectronics , 2003 .

[18]  Ming Zhang,et al.  On the Scalability of Redundancy based SER Mitigation Schemes , 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.