Stochastic decoding of LDPC codes

This letter presents the first successful method for iterative stochastic decoding of state-of-the-art low-density parity-check (LDPC) codes. The proposed method shows the viability of the stochastic approach for decoding LDPC codes on factor graphs. In addition, simulation results for a 200 and a 1024 length LDPC code demonstrate the near-optimal performance of this method with respect to sum-product decoding. The proposed method has a significant potential for high-throughput and/or low complexity iterative decoding.

[1]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[2]  Brian R. Gaines.  Advances in information systems science , 1969 .

[3]  Brian R. Gaines,et al.  Stochastic Computing Systems , 1969 .

[4]  J. Tou.  Advances in Information Systems Science , 1970, Springer US.

[5]  Brendan J. Frey,et al.  Factor graphs and the sum-product algorithm , 2001, IEEE Trans. Inf. Theory.

[6]  Howard C. Card,et al.  Stochastic Neural Computation I: Computational Elements , 2001, IEEE Trans. Computers.

[7]  Rüdiger L. Urbanke,et al.  The capacity of low-density parity-check codes under message-passing decoding , 2001, IEEE Trans. Inf. Theory.

[8]  C. Winstead.  Stochastic Iterative Decoding on Factor Graphs , 2003 .

[9]  Vincent C. Gaudet,et al.  Analog iterative decoding of error control codes , 2003, CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH37436).

[10]  Vincent C. Gaudet,et al.  Iterative decoding using stochastic computation , 2003 .

[11]  W.J. Gross,et al.  Stochastic Implementation of LDPC Decoders , 2005, Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005..

[12]  Vincent C. Gaudet,et al.  Stochastic iterative decoders , 2005, Proceedings. International Symposium on Information Theory, 2005. ISIT 2005..

[13]  Nhan Nguyen,et al.  Low-voltage CMOS circuits for analog iterative decoders , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.