S. D. Haynes

Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAs

Peter Y. K. Cheung, S. D. Haynes, A. B. Ferrari, 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

Configurable multiplier blocks for embedding in FPGAs

Peter Y. K. Cheung, S. D. Haynes, 1998 .

UltraSONIC: A Reconfigurable Architecture for Video Image Processing

S. D. Haynes, Simon D. Haynes, Henry G. Epsom, 2002, FPL.