Energy-Efficient Discrete Cosine Transform on FPGAs

The 2-D discrete cosine transform (DCT) is an integral part of video and image processing;it is used in both the JPEG and MPEG encoding standards. As streaming video is brought to mobile devices, it becomesimportant that it is possible to calculate the DCT in an energy-efficient manner. In this paper, we presenta new algorithm and processingelement (PE) architecture for computing the DCT with a linear array of PEs. This design is optimized for energy efficiency. We analyze the energy, area, and latency tradeoffs available with this design and then compare its energy dissipation, area, and latency to those of Xilinx’ s optimized IP core.