Direct Compare of Information Coded With Error-Correcting Codes
暂无分享,去创建一个
[1] Mark Horowitz,et al. Clustered voltage scaling technique for low-power design , 1995, ISLPED '95.
[2] Bo Yang,et al. Statistical prediction of circuit aging under process variations , 2008, 2008 IEEE Custom Integrated Circuits Conference.
[3] Yehea I. Ismail,et al. Statistical static timing analysis: how simple can we get? , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[4] Eiji Fujiwara,et al. Error-control coding for computer systems , 1989 .
[5] Hideaki Kobayashi,et al. A Synthesizing Method for Large Parallel Counters with a Network of Smaller Ones , 1978, IEEE Transactions on Computers.
[6] Caxton C. Foster,et al. Counting Responders in an Associative Memory , 1971, IEEE Transactions on Computers.
[7] Yu Wang,et al. Variation-aware supply voltage assignment for minimizing circuit degradation and leakage , 2009, ISLPED.
[8] Wei Chen,et al. The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series , 2007, IEEE Journal of Solid-State Circuits.
[9] Rong Luo,et al. Leakage power reduction through dual Vth assignment considering threshold voltage variation , 2007, 2007 7th International Conference on ASIC.
[10] Yu Cao,et al. Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology , 2007, IEEE Transactions on Device and Materials Reliability.
[11] Hiroyuki Sugiyama,et al. A 1.3 GHz fifth generation SPARC64 microprocessor , 2003 .
[12] Earl E. Swartzlander. A review of large parallel counter designs , 2004, IEEE Computer Society Annual Symposium on VLSI.
[13] Yu Cao,et al. Predictive Modeling of the NBTI Effect for Reliable Design , 2006, IEEE Custom Integrated Circuits Conference 2006.
[14] Earl E. Swartzlander. Parallel Counters , 1973, IEEE Transactions on Computers.