A generalized conflict-free address scheme for arbitrary 2k-point memory-based FFT processors

This paper presents an efficient conflict-free memory address scheme for arbitrary 2k-point memory-based FFT processors. The address scheme can support in-place strategy, continuous-flow mode, and variable size for arbitrary long sized FFT. More over, the address scheme can adjust the throughput by changing the computation radix and the parallelism of the arithmetic processing units according to the specific implementation requirements. We have designed a configurable 128 — 2048 point FFT processor for LTE system. From the results, we can see the proposed address scheme has excellent point flexibility, hardware efficiency, and can support almost any 2k-point FFT implementations.

[1]  Hanho Lee,et al.  A High-Speed Low-Complexity Modified ${\rm Radix}-2^{5}$ FFT Processor for High Rate WPAN Applications , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Chao-Ming,et al.  Energy-efficient 128∼2048/1536-point FFT processor with resource block mapping for 3GPP-LTE system , 2010 .

[3]  Chao Wang,et al.  A High-Throughput Low-Complexity Radix- $2^{\textbf {4}}$ - $2^{\textbf {2}}$ - $2^{\textbf {3}}$ FFT/IFFT Processor With Parallel and Normal Input/Output Order for IEEE 802.11ad Systems , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Dejan Markovic,et al.  Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example , 2012, IEEE Journal of Solid-State Circuits.

[5]  Pei-Yun Tsai,et al.  A Generalized Conflict-Free Memory Addressing Scheme for Continuous-Flow Parallel-Processing FFT Processors With Rescheduling , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Myung Hoon Sunwoo,et al.  Novel Shared Multiplier Scheduling Scheme for Area-Efficient FFT/IFFT Processors , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Sau-Gee Chen,et al.  A High-Throughput Radix-16 FFT Processor With Parallel and Normal Input/Output Ordering for IEEE 802.15.3c Systems , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Myung Hoon Sunwoo,et al.  New continuous-flow mixed-radix (CFMR) FFT Processor using novel in-place strategy , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  Narayanan Vijaykrishnan,et al.  Multidimensional DFT IP Generator for FPGA Platforms , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Chu Yu,et al.  Area-Efficient 128- to 2048/1536-Point Pipeline FFT Processor for LTE and Mobile WiMAX Systems , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Lewis Johnson,et al.  Conflict free memory addressing for dedicated FFT hardware , 1992 .

[12]  Kiyoung Choi,et al.  New address generation scheme for memory-based FFT processor using multiple radix-2 butterflies , 2008, 2008 International SoC Design Conference.