Relaxation Dynamics in Stochastic Iterative Decoders
暂无分享,去创建一个
Shie Mannor | Vincent C. Gaudet | Warren J. Gross | Chris Winstead | Sheryl L. Howard | Saeed Sharifi Tehrani | S. L. Howard | Shie Mannor | S. Tehrani | W. Gross | C. Winstead | V. Gaudet
[1] Vincent C. Gaudet,et al. Stochastic iterative decoders , 2005, Proceedings. International Symposium on Information Theory, 2005. ISIT 2005..
[2] Vincent C. Gaudet,et al. Iterative decoding using stochastic computation , 2003 .
[3] A. J. Blanksby,et al. A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.
[4] Ran-Hong Yan,et al. A unified turbo/viterbi channel decoder for 3GPP mobile wireless in 0.18 /spl mu/m CMOS , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[5] Shie Mannor,et al. An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding , 2007, 2007 IEEE Workshop on Signal Processing Systems.
[6] Hua Xiao,et al. Successive relaxation for decoding of LDPC codes , 2008, 2008 24th Biennial Symposium on Communications.
[7] Craig B. Zilles,et al. Probabilistic counter updates for predictor hysteresis and bias , 2006, IEEE Computer Architecture Letters.
[8] J. Tou. Advances in Information Systems Science , 1970, Springer US.
[9] D. ForneyG.,et al. Codes on graphs , 2006 .
[10] Brian R. Gaines,et al. Stochastic Computing Systems , 1969 .
[11] Howard C. Card,et al. Stochastic Neural Computation I: Computational Elements , 2001, IEEE Trans. Computers.
[12] Bo Zhu,et al. Stochastic Decoding of Linear Block Codes With High-Density Parity-Check Matrices , 2008, IEEE Transactions on Signal Processing.
[13] Frank R. Kschischang,et al. Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.
[14] Amir H. Banihashemi,et al. On the dynamics of continuous-time analog iterative decoding , 2004, International Symposium onInformation Theory, 2004. ISIT 2004. Proceedings..
[15] D BrownBradley,et al. Stochastic Neural Computation II , 2001 .
[16] C. Chakrabarti,et al. Design and implementation of low-energy turbo decoders , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[17] M. Harrison,et al. Advances in Information Systems Science , 1981, Springer US.
[18] Mohammad M. Mansour,et al. A 640-Mb/s 2048-bit programmable LDPC decoder chip , 2006, IEEE Journal of Solid-State Circuits.
[19] Amir H. Banihashemi,et al. Dynamics and performance analysis of analog iterative decoding for low-density parity-check (LDPC) codes , 2006, IEEE Transactions on Communications.
[20] Brendan J. Frey,et al. Factor graphs and the sum-product algorithm , 2001, IEEE Trans. Inf. Theory.
[21] A. Blanksby,et al. A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.
[22] C. Kelley. Iterative Methods for Linear and Nonlinear Equations , 1987 .
[23] G. Forney,et al. Codes on graphs: normal realizations , 2000, 2000 IEEE International Symposium on Information Theory (Cat. No.00CH37060).
[24] Shie Mannor,et al. Stochastic decoding of LDPC codes , 2006, IEEE Communications Letters.
[25] Shie Mannor,et al. Fully Parallel Stochastic LDPC Decoders , 2008, IEEE Transactions on Signal Processing.
[26] James M. Ortega,et al. Iterative solution of nonlinear equations in several variables , 2014, Computer science and applied mathematics.
[27] Pierre L'Ecuyer,et al. Tables of maximally equidistributed combined LFSR generators , 1999, Math. Comput..