Energy efficiency of FPGAs and programmable processors for matrix multiplication
暂无分享,去创建一个
[1] Viktor K. Prasanna,et al. Area and time efficient implementations of matrix multiplication on FPGAs , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..
[2] Sujit Dey,et al. High-Level Power Analysis and Optimization , 1997 .
[3] Li Shang,et al. Dynamic power consumption in Virtex™-II FPGA family , 2002, FPGA '02.
[4] Gary K. Yeap,et al. Practical Low Power Digital VLSI Design , 1997 .
[5] Benjamin W. Wah,et al. Systematic approaches to the design of algorithmically specified systolic arrays , 1985, ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing.
[6] Viktor K. Prasanna,et al. Energy-Efficient Matrix Multiplication on FPGAs , 2002, FPL.
[7] André DeHon,et al. The Density Advantage of Configurable Computing , 2000, Computer.
[8] Russell Tessier,et al. Reconfigurable Computing for Digital Signal Processing: A Survey , 2001, J. VLSI Signal Process..
[9] Majid Sarrafzadeh,et al. An effective algorithm for gate-level power-delay tradeoff using two voltages , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).
[10] Michael J. Flynn,et al. Hardware software tri-design of encryption for mobile communication units , 1998, Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181).
[11] A.D. Garcia G.,et al. Reducing the power consumption in FPGAs with keeping a high performance level , 2000, Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era.