Fully Parallel Stochastic LDPC Decoders

Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stochastic low-density parity-check (LDPC) decoders. To obtain the characteristics of the proposed architecture, we apply this architecture to decode an irregular state-of-the-art (1056,528) LDPC code on a Xilinx Virtex-4 LX200 field-programmable gate-array (FPGA) device. The implemented decoder achieves a clock frequency of 222 MHz and a throughput of about 1.66 Gb/s at Eb/N0=4.25 dB (a bit error rate of 10-8). It provides decoding performance within 0.5 and 0.25 dB of the floating-point sum-product algorithm with 32 and 16 iterations, respectively, and similar error-floor behavior. The decoder uses less than 40% of the lookup tables, flip-flops, and IO ports available on the FPGA device. The results provided in this paper validate the potential of stochastic LDPC decoding as a practical and competitive fully parallel decoding approach.

[1]  Christian Schlegel,et al.  Trellis and turbo coding , 2004 .

[2]  W.J. Gross,et al.  Stochastic Implementation of LDPC Decoders , 2005, Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005..

[3]  M. Moerz,et al.  An analog 0.25 /spl mu/m BiCMOS tailbiting MAP decoder , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[4]  Zhongfeng Wang,et al.  Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  C. Winstead.  Stochastic Iterative Decoding on Factor Graphs , 2003 .

[6]  M. Harrison,et al.  Advances in Information Systems Science , 1981, Springer US.

[7]  Guido Masera,et al.  Implementation of a Flexible LDPC Decoder , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[8]  Stephen G. Wilson,et al.  Multi-Gbps FPGA-Based Low Density Parity Check (LDPC) Decoder Design , 2007, IEEE GLOBECOM 2007 - IEEE Global Telecommunications Conference.

[9]  P. Urard,et al.  A 135Mb/s DVB-S2 compliant codec based on 64800b LDPC and BCH codes , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[10]  X. Jin.  Factor graphs and the Sum-Product Algorithm , 2002 .

[11]  A. Neviani,et al.  A 0.35-/spl mu/m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code , 2005, IEEE Journal of Solid-State Circuits.

[12]  Vincent C. Gaudet,et al.  A degree-matched check node approximation for LDPC decoding , 2005, Proceedings. International Symposium on Information Theory, 2005. ISIT 2005..

[13]  Radford M. Neal,et al.  Near Shannon limit performance of low density parity check codes , 1996 .

[14]  Chaitali Chakrabarti,et al.  Design and Analysis of LDPC Decoders for Software Defined Radio , 2007, 2007 IEEE Workshop on Signal Processing Systems.

[15]  Naresh R. Shanbhag,et al.  High-throughput LDPC decoders , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[16]  Niclas Wiberg,et al.  Codes and Decoding on General Graphs , 1996 .

[17]  Vincent C. Gaudet,et al.  Stochastic iterative decoders , 2005, Proceedings. International Symposium on Information Theory, 2005. ISIT 2005..

[18]  Frank R. Kschischang,et al.  A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[19]  Amir H. Banihashemi,et al.  Improving belief propagation on graphs with cycles , 2004, IEEE Communications Letters.

[20]  Tong Zhang,et al.  Joint (3,k)-regular LDPC code and decoder/encoder design , 2004, IEEE Transactions on Signal Processing.

[21]  Achilleas Anastasopoulos,et al.  A comparison between the sum-product and the min-sum iterative detection algorithms based on density evolution , 2001, GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No.01CH37270).

[22]  Brian R. Gaines,et al.  Stochastic Computing Systems , 1969 .

[23]  George S. Moschytz,et al.  All–analog decoder for a binary (18,9,5) tail–biting trellis code , 1999 .

[24]  Venkat Anantharam,et al.  Iterative decoder architectures , 2003, IEEE Commun. Mag..

[25]  Vincent C. Gaudet,et al.  Decoder IC with a Configurable Interleaver , 2003 .

[26]  Frank R. Kschischang,et al.  Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[27]  Joachim Hagenauer,et al.  WA 21.5 An Analog 0.25∝m BiCMOS Tailbiting MAP Decoder , 2000 .

[28]  Vincent C. Gaudet,et al.  Iterative decoding using stochastic computation , 2003 .

[29]  Marc P. C. Fossorier,et al.  A modified weighted bit-flipping decoding of low-density Parity-check codes , 2004, IEEE Communications Letters.

[30]  Judea Pearl,et al.  Probabilistic reasoning in intelligent systems - networks of plausible inference , 1991, Morgan Kaufmann series in representation and reasoning.

[31]  Jean-Luc Danger,et al.  Lambda-Min Decoding Algorithm of Regular and Irregular LDPC Codes , 2003 .

[32]  Brendan J. Frey,et al.  Factor graphs and the sum-product algorithm , 2001, IEEE Trans. Inf. Theory.

[33]  Bruce F. Cockburn,et al.  A scalable LDPC decoder ASIC architecture with bit-serial message exchange , 2008, Integr..

[34]  Rüdiger L. Urbanke,et al.  The capacity of low-density parity-check codes under message-passing decoding , 2001, IEEE Trans. Inf. Theory.

[35]  T. Hanyu,et al.  3.2-Gb/s 1024-b rate-1/2 LDPC decoder chip using a flooding-type update-schedule algorithm , 2007, 2007 50th Midwest Symposium on Circuits and Systems.

[36]  P.G. Gulak,et al.  A 13.3Mb/s 0.35/spl mu/m CMOS analog turbo decoder IC with a configurable interleaver , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[37]  Shie Mannor,et al.  Stochastic decoding of LDPC codes , 2006, IEEE Communications Letters.

[38]  Amir H. Banihashemi,et al.  A Differential Binary Message-Passing LDPC Decoder , 2007, IEEE GLOBECOM 2007 - IEEE Global Telecommunications Conference.

[39]  J. Tou.  Advances in Information Systems Science , 1970, Springer US.

[40]  Shie Mannor,et al.  Survey of Stochastic Computation on Factor Graphs , 2007, 37th International Symposium on Multiple-Valued Logic (ISMVL'07).

[41]  Ajay Dholakia,et al.  Reduced-complexity decoding of LDPC codes , 2005, IEEE Transactions on Communications.

[42]  R.R. Harrison,et al.  CMOS analog MAP decoder for (8,4) Hamming code , 2004, IEEE Journal of Solid-State Circuits.

[43]  C. Plett,et al.  A 0.18-$muhbox m$CMOS Analog Min-Sum Iterative Decoder for a (32,8) Low-Density Parity-Check (LDPC) Code , 2006, IEEE Journal of Solid-State Circuits.

[44]  Frank R. Kschischang,et al.  A bit-serial approximate min-sum LDPC decoder and FPGA implementation , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[45]  Mohammad M. Mansour,et al.  A 640-Mb/s 2048-bit programmable LDPC decoder chip , 2006, IEEE Journal of Solid-State Circuits.

[46]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[47]  A. J. Blanksby,et al.  A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.

[48]  A. Blanksby,et al.  A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.

[49]  Frank R. Kschischang,et al.  Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[50]  Fabrice Seguin,et al.  Analog slice turbo decoding , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[51]  Ming Jiang,et al.  An improvement on the modified weighted bit flipping decoding algorithm for LDPC codes , 2005, IEEE Communications Letters.

[52]  Mohammed Atiquzzaman,et al.  VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax , 2007, 2007 IEEE International Conference on Communications.

[53]  Shie Mannor,et al.  An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding , 2007, 2007 IEEE Workshop on Signal Processing Systems.