Models and reconfiguration problems for multi task hyperreconfigurable architectures

Summary form only given. Hyperreconfigurable architectures can adapt their reconfiguration abilities during run time and have been proposed to increase the speed of dynamic reconfiguration. They use two types of dynamic reconfiguration steps. In hyperreconfiguration steps they change their ability for reconfiguration and in ordinary reconfiguration steps they reconfigure the actual contexts for a computation within the limits that have been set by the last hyperreconfiguration step. We study the concept of partial hyperreconfiguration for multi tasks environments. We propose several models for partially hyperreconfigurable architectures and study corresponding reconfiguration problems to find optimal (hyper)reconfigurations. While under a general cost model the problem to find optimal (hyper)reconfigurations is known to be NP-complete even for a single task. We identify an interesting special case that can be solved by a polynomial time algorithm even for multiple tasks. We illustrate the introduced concepts with a partially hyperreconfigurable example architecture and describe the results of simulated runs with a small test application.

[1]  Zhiyuan Li,et al.  Configuration compression for the Xilinx XC6200 FPGA , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[2]  Martin Middendorf,et al.  The Partition into Hypercontexts Problem for Hyperreconfigurable Architectures , 2004, FPL.

[3]  Jörg Henkel,et al.  Dynamic runtime re-scheduling allowing multiple implementations of a task for platform-based designs , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[4]  Viktor K. Prasanna,et al.  Reconfigurable computing: Architectures, mod- els and algorithms , 2000 .

[5]  Malgorzata Marek-Sadowska,et al.  Interconnect resource-aware placement for hierarchical FPGAs , 2001, ICCAD.

[6]  Viktor K. Prasanna,et al.  A Self-Reconfigurable Gate Array Architecture , 2000, FPL.

[7]  Andreas Dandalis,et al.  Efficient Self-Reconfigurable Implementations Using On-chip Memory , 2000, FPL.

[8]  Dinesh Bhatia,et al.  On metrics for comparing routability estimation methods for FPGAs , 2002, DAC '02.

[9]  Scott Hauck,et al.  Reconfigurable computing: a survey of systems and software , 2002, CSUR.

[10]  Viktor K. Prasanna,et al.  Configuration compression for FPGA-based embedded systems , 2005, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Jürgen Teich,et al.  (Self-)reconfigurable finite state machines: theory and implementation , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[12]  Jürgen Teich,et al.  Compile-time Optimization of Dynamic Hardware Reconfigurations , 1999, PDPTA.

[13]  Abdel Ejnioui,et al.  Routing on switch matrix multi-FPGA systems , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[14]  Martin Middendorf,et al.  Hyperreconfigurable architectures and the partition into hypercontexts problem , 2005, J. Parallel Distributed Comput..

[15]  Martin D. F. Wong,et al.  Incremental reconfiguration of multi-FPGA systems , 2002, FPGA '02.

[16]  Christian Haubelt,et al.  System design for flexibility , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.