Hyperreconfigurable Architectures as Flexible Control Systems

Hyperreconfigurable architectures can change their reconfiguration capabilities dynamically at run-time. For reconfiguration they use two types of reconfiguration steps: i) in hyperreconfiguration steps they change their ability for reconfiguration, ii) in ordinary reconfiguration steps they reconfigure the actual contexts of a computation within the limits that have been set by the preceding hyperreconfiguration step. Hyperreconfigurable architectures have originally been introduced to increase the speed of run-time reconfiguration. In this paper we show that the high flexibility with respect to runtime reconfiguration makes hyperreconfigurable architectures well suited for the control of processes that demand varying amounts of supervision. One advantage of hyperreconfiguration is that the run-time of a control task can be influenced without changing the task itself but only by using different variants of other control tasks that run in parallel. To illustrate the concepts we present the results of simulations with a small hyperreconfigurable architecture where counter and adder control tasks run in parallel.

[1]  Zhiyuan Li,et al.  Configuration compression for the Xilinx XC6200 FPGA , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[2]  Viktor K. Prasanna,et al.  Configuration compression for FPGA-based embedded systems , 2005, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Jürgen Teich,et al.  (Self-)reconfigurable finite state machines: theory and implementation , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[4]  Andreas Dandalis,et al.  Efficient Self-Reconfigurable Implementations Using On-chip Memory , 2000, FPL.

[5]  Viktor K. Prasanna,et al.  A Self-Reconfigurable Gate Array Architecture , 2000, FPL.

[6]  Martin D. F. Wong,et al.  Incremental reconfiguration of multi-FPGA systems , 2002, FPGA '02.

[7]  Martin Middendorf,et al.  Hyperreconfigurable architectures and the partition into hypercontexts problem , 2005, J. Parallel Distributed Comput..

[8]  Wayne P. Burleson,et al.  Configuration cloning: exploiting regularity in dynamic DSP architectures , 1999, FPGA '99.