Efficient Metacomputation Using Self-Reconfiguration

Self-reconfiguration is a technique using which configured logic can quickly modify itself at runtime to suit application requirements. Although performance improvements using self-reconfiguration have been demonstrated, the technique itself has been only informally described. Based on an abstract reconfigurable device model, a precise definition of self-reconfiguration is presented in this paper. Various practical issues in efficiently implementing self-reconfiguration are also discussed.A competing approach to self-reconfiguration is the use of a von Neumann processor on the same chip as the reconfigurable logic. Both alternatives can provide on-chip configuration modification. The performance of both alternatives is evaluated for a frequently used configuration modification operation. The approaches used for both alternatives are described and the performance of both approaches is evaluated. Self-reconfiguration is found to require significantly lesser area as well as significantly lesser time compared to the attached processor approach.

[1]  Anant Agarwal,et al.  Solving graph problems with dynamic computation structures , 1996, Other Conferences.

[2]  Viktor K. Prasanna,et al.  String matching on multicontext FPGAs using self-reconfiguration , 1999, FPGA '99.

[3]  R. W. Taylor,et al.  A self-reconfiguring processor , 1993 .

[4]  Viktor K. Prasanna,et al.  Fast Regular Expression Matching Using FPGAs , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[5]  Ben J Hicks,et al.  SPIE - The International Society for Optical Engineering , 2001 .

[6]  Viktor K. Prasanna,et al.  Genetic Programming Using Self-Reconfigurable FPGAs , 1999, FPL.

[7]  Viktor K. Prasanna,et al.  A Self-Reconfigurable Gate Array Architecture , 2000, FPL.

[8]  Adam Donlin,et al.  Self Modifying Circuitry - A Platform for Tractable Virtual Circuitry , 1998, FPL.

[9]  R. W. Taylor,et al.  A self-reconfigurable processor , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.