VIP : An FPGA-based Processor for Image Processingand Neural

We present in this paper the architecture and implementation of the Virtual Image Processor (VIP) which is an SIMD multiprocessor build with large FPGAs. The SIMD architecture, together with a 2D torus connection topology, is well suited for image processing, pattern recognition and neural network algorithms. The VIP board can be programmed on-line at the logic level, allowing optimal hardware dedication to any given algorithm. Even with the last decades exponential growth in performance of integrated circuits, many image processing and neural network applications still demand increased hardware speed. A rst approach to increase performance is to build massively parallel computers. Their high price and diiculty to program have resulted in a very low acceptance rate. The design cycle of those computers is usually too long, and thus their technology is obsolete before they are commercially available. Consequently, users often prefer to use the latest high performance general workstation that is much less expensive and more easy to program. A second approach to solve the performance problem is to design dedicated parallel hardware for one task (or set of similar tasks). Their programmation is usually simple (or even nonexistent) while their performance/cost ratio is high. However, they are not exible and their design cycle is long. Over the last few years, advances in programmable logic devices have resulted in the commercialization of eld programmable gate arrays (FPGA) which allow to put large numbers of programmable logic elements on a single chip. The size and speed of those circuits improve at the same rate as microprocessors' size and speed, since they rely on the same technology. In section 2, we propose an architectural framework for the virtual image processor (VIP) which is a parallel processor having large FPGAs as main components. In section 3, we present the rst prototype of the VIP board that uses 5 large FPGAs, has 1.5 MB of static RAM and communicates through a fast PCI bus. We are currently targeting at applications requiring a large number of simple low precision operations. Many commerciallyattractive applications fall into this category such as image processing and pattern recognition (e.g., recognition of fax documents, bank checks, postal addresses). Those applications are particularly well suited for FPGA implementation since a simple processing element (PE) may perform their most basic operations. Consequently, many instances of this PE may be tted on one FPGA. We present in section 4 two algorithms that fall …

[1]  H. T. Kung,et al.  Systolic Arrays for (VLSI). , 1978 .

[2]  Lawrence D. Jackel,et al.  Application of the ANNA neural network chip to high-speed character recognition , 1992, IEEE Trans. Neural Networks.

[3]  E. Cosatto,et al.  NET32K high speed image understanding system , 1994, Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems.

[4]  E. Sackinger,et al.  A system for high-speed pattern recognition and image analysis , 1994, Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems.

[5]  J. Cloutier,et al.  Hardware implementation of the backpropagation without multiplication , 1994, Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems.