Bidirectional interleavers for LDPC decoders using transmission gates
暂无分享,去创建一个
[1] Bernhard Hoppe,et al. Transmission gate delay models for circuit optimization , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..
[2] C. R. Henson. Conclusion , 1969 .
[3] Joseph R. Cavallaro,et al. Multi-Rate High-Throughput LDPC Decoder: Tradeoff Analysis Between Decoding Throughput and Area , 2006, 2006 IEEE 17th International Symposium on Personal, Indoor and Mobile Radio Communications.
[4] Tinoosh Mohsenin,et al. Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture , 2006, 2006 International Conference on Computer Design.
[5] Shie Mannor,et al. Fully Parallel Stochastic LDPC Decoders , 2008, IEEE Transactions on Signal Processing.
[6] Frank Kienle,et al. Disclosing the LDPC code decoder design space , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[7] Vincent C. Gaudet,et al. Iterative decoding using stochastic computation , 2003 .
[8] Luca Fanucci,et al. Multi-size circular shifting networks for decoders of structured LDPC codes , 2007 .
[9] Hsie-Chia Chang,et al. Multi-mode message passing switch networks applied for QC-LDPC decoder , 2008, 2008 IEEE International Symposium on Circuits and Systems.
[10] Naresh R. Shanbhag,et al. Architecture-aware low-density parity-check codes , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..
[11] Zhongfeng Wang,et al. Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders , 2009, IEEE Trans. Circuits Syst. II Express Briefs.
[12] A. J. Blanksby,et al. A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.
[13] Frank R. Kschischang,et al. Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.
[14] Frank R. Kschischang,et al. A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS , 2007, 2007 IEEE Custom Integrated Circuits Conference.
[15] Radford M. Neal,et al. Near Shannon limit performance of low density parity check codes , 1996 .