Test Architecture for Fine Grained Capture Power Reduction

Excessive power during in–field testing can cause multiple issues, including invalidation of the test results, over- heating, and damage to the circuit. In this paper, we evaluate the reduction of capture power when specific segments of a scan chain can be kept from capturing data subject to values stored in a control register. The proposed approach requires no changes to the Automatic Test Pattern Generation (ATPG), no redesign of the circuitry to match a particular test set, and no additional patterns to maintain fault coverage. We will show that our approach can achieve very high capture power reduction-approaching 100% for multiple patterns.

[1]  Nilanjan Mukherjee,et al.  Compression based on deterministic vector clustering of incompatible test cubes , 2009, 2009 International Test Conference.

[2]  Weizheng Wang,et al.  Achieving low capture and shift power in linear decompressor-based test compression environment , 2012, Microelectron. J..

[3]  Atul K. Jain,et al.  Minimizing power consumption in scan testing: pattern generation and DFT techniques , 2004 .

[4]  P. Wilson,et al.  At-speed capture power reduction using layout-aware granular clock gate enable controls , 2014, 2014 International Test Conference.

[5]  Janusz Rajski,et al.  Low Power Decompressor and PRPG with Constant Value Broadcast , 2011, 2011 Asian Test Symposium.

[6]  Kozo Kinoshita,et al.  Low-capture-power test generation for scan-based at-speed testing , 2005, IEEE International Conference on Test, 2005..

[7]  Hideo Fujiwara,et al.  Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power , 2010, 2010 19th IEEE Asian Test Symposium.

[8]  Kaushik Roy,et al.  Low-power scan design using first-level supply gating , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Lung-Jen Lee,et al.  Deterministic ATPG for Low Capture Power Testing , 2012, 2012 13th International Workshop on Microprocessor Test and Verification (MTV).

[10]  Nilanjan Mukherjee,et al.  Low capture power at-speed test in EDT environment , 2010, 2010 IEEE International Test Conference.

[11]  Hideo Fujiwara,et al.  A Low Power Deterministic Test Using Scan Chain Disable Technique , 2006, IEICE Trans. Inf. Syst..

[12]  Vishwani D. Agrawal,et al.  On Minimization of Peak Power for Scan Circuit during Test , 2009, 2009 14th IEEE European Test Symposium.

[13]  Irith Pomeranz,et al.  On generating pseudo-functional delay fault tests for scan designs , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[14]  Lee Whetsel,et al.  Adapting scan architectures for low power operation , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[15]  Xiaoqing Wen,et al.  Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  Arnaud Virazel,et al.  Test of low power circuits: Issues and industrial practices , 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

[17]  Yiorgos Tsiatouhas,et al.  Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique , 2014, J. Electron. Test..

[18]  Janusz Rajski,et al.  Low-Power Scan Operation in Test Compression Environment , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.