Fast Online Set Intersection for Network Processing on FPGA

Online set intersection operations have been widely used in network processing tasks, such as Quality of Service differentiation, firewall processing, and packet/traffic classification. The major challenge for online set intersection is to sustain line-rate processing speed; accelerating set intersection using state-of-the-art hardware devices is of great interest to the research community. In this paper, we present a novel high-performance set intersection approach on FPGA. In our approach, each element in any set is represented by a combination of Group ID (GID) and Bit Stride (BS); all the sets are intersected using linear merge techniques and bitwise AND operations. We map our online set intersection algorithm onto hardware; this is done by constructing modular Processing Element (PE) and concatenating multiple PEs into a tree-based parallel architecture. In order to improve the throughput on a state-of-the-art FPGA, we feed all the inputs to FPGA in a streaming fashion with the help of the synchronization GIDs. Post place-and-route results show that, for a typical set intersection problem in network processing, our design can intersect <inline-formula><tex-math notation="LaTeX">$\text{eight}$</tex-math><alternatives> <inline-graphic xlink:type="simple" xlink:href="qu-ieq1-2537818.gif"/></alternatives></inline-formula> sets, each of up to <inline-formula> <tex-math notation="LaTeX">$32$</tex-math><alternatives><inline-graphic xlink:type="simple" xlink:href="qu-ieq2-2537818.gif"/> </alternatives></inline-formula>K elements, at a throughput of <inline-formula><tex-math notation="LaTeX"> $47.4$</tex-math><alternatives><inline-graphic xlink:type="simple" xlink:href="qu-ieq3-2537818.gif"/></alternatives> </inline-formula> Thousand Intersections Per Second (KIPS) and a latency of <inline-formula><tex-math notation="LaTeX"> $94.8\,\mu$</tex-math><alternatives><inline-graphic xlink:type="simple" xlink:href="qu-ieq4-2537818.gif"/></alternatives> </inline-formula>s per batch of inputs. Compared to the classic linear merge or bitwise AND techniques on state-of-the-art multi-core processors, our designs on FPGA achieves up to <inline-formula><tex-math notation="LaTeX"> $66\times$</tex-math><alternatives><inline-graphic xlink:type="simple" xlink:href="qu-ieq5-2537818.gif"/></alternatives> </inline-formula> throughput improvement and <inline-formula><tex-math notation="LaTeX">$80\times$ </tex-math><alternatives><inline-graphic xlink:type="simple" xlink:href="qu-ieq6-2537818.gif"/></alternatives></inline-formula> latency reduction.

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