Hardware Object Selection for Mapping Loops onto Reconfigurable Architectures

Reconngurable circuits and systems have evolved from application speciic accelerators to a general purpose computing paradigm. Re-connguring the logic is still an expensive operation and precludes frequent connguration changes. To reduce the overheads involved in reconnguration, devices with connguration caches and multiple contexts are being designed. Reconngurable computing solutions are typically designed by composing lower level modules or library components. Each operation in an application can be implemented by using any one among several of these modules or hardware objects. This gives rise to the problem of choosing an optimal set of modules for utilizing the cache or the multiple contexts. This paper develops a formal methodology for selection of these modules to minimize the total execution time. The total execution time includes the reconnguration time and the computation time in various conngurations. We focus on loop computations since they are the most compute intensive parts of applications. We utilize a parameterized abstract model of reconngurable architectures which is general enough to capture a wide range of conngurable systems. Our abstract model is used to de-ne the problem of mapping loop statements onto reconngurable architectures. We show a polynomial time algorithm to compute the optimal sequence of conngurations(modules) for one important variant of the problem.