Reconfigurable computing systems

Reconfigurable computing is emerging as the new paradigm for satisfying the simultaneous demand for application performance and flexibility. The ability to customize the architecture to match the computation and the data flow of the application has demonstrated significant performance benefits compared to general purpose architectures. Computer vision applications are one class of applications that have significant heterogeneity in their computation and communication structures. At the low level, vision algorithms have regular repetitive computations operating on large sets of image data with predictable data dependencies. At the higher level, the computations have irregular dependencies. Computer vision application characteristics have significant overlap with the advantages of reconfigurable architectures. The main focus of the paper is on outlining the methodologies required to realize the potential of reconfigurable architectures for vision applications. After giving a broad introduction to reconfigurable computing, the advantages of utilizing reconfigurable architectures for vision applications are outlined and illustrated using example computations. The paper discusses the development of fundamental configurable computing models that abstract the underlying hardware for high-level application mapping. The Hybrid System Architecture Model and algorithms utilizing the model are illustrated to demonstrate a formal framework. The paper also outlines ongoing research and provides a comprehensive list of references for further reading.

[1]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[2]  P.M. Athanas,et al.  Real-Time Image Processing on a Custom Computing Platform , 1995, Computer.

[3]  Santosh Pande,et al.  Automatic Analysis of Loops to Exploit Operator Parallelism on Reconfigurable Systems , 1998, LCPC.

[4]  Peter M. Athanas,et al.  Wormhole run-time reconfiguration , 1997, FPGA '97.

[5]  Vivek Sarkar,et al.  Baring It All to Software: Raw Machines , 1997, Computer.

[6]  Mark Shand,et al.  Programmable active memories: reconfigurable systems come of age , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[7]  Viktor K. Prasanna,et al.  Genetic Programming Using Self-Reconfigurable FPGAs , 1999, FPL.

[8]  Kiran Bondalapati.  Parallelizing DSP nested loops on reconfigurable architectures using data context switching , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[9]  A. Lynn Abbott,et al.  Implementation of a 2-D Fast Fourier Transform on an FPGA-Based Custom Computing Machine , 1995, FPL.

[10]  Anant Agarwal,et al.  Solving graph problems with dynamic computation structures , 1996, Other Conferences.

[11]  Majid Sarrafzadeh,et al.  A quick safari through the reconfiguration jungle , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[12]  Bruce A. Draper,et al.  Precision vs. error in JPEG compression , 1999, Optics + Photonics.

[13]  Viktor K. Prasanna,et al.  Configurable hardware for symbolic search operations , 1997, Proceedings 1997 International Conference on Parallel and Distributed Systems.

[14]  Brad L. Hutchings,et al.  JHDL-an HDL for reconfigurable systems , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[15]  John Woodfill,et al.  Real-time stereo vision on the PARTS reconfigurable computer , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[16]  John Wawrzynek,et al.  Instruction-Level Parallelism for Reconfigurable Computing , 1998, FPL.

[17]  Viktor K. Prasanna,et al.  Mapping Loops onto Reconfigurable Architectures , 1998, FPL.

[18]  Rob Payne.  Run-time parameterised circuits for the Xilinx XC6200 , 1997, FPL.

[19]  Seth Copen Goldstein,et al.  Managing pipeline-reconfigurable FPGAs , 1998, FPGA '98.

[20]  Viktor K. Prasanna,et al.  Dynamic precision management for loop computations on reconfigurable architectures , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[21]  Viktor K. Prasanna,et al.  Domain Specific Mapping for Solving Graph Problems on Reconfigurable Devices , 1999, IPPS/SPDP Workshops.

[22]  Wayne Luk,et al.  Pipeline morphing and virtual pipelines , 1997, FPL.

[23]  Carl Ebeling,et al.  RaPiD - Reconfigurable Pipelined Datapath , 1996, FPL.

[24]  Maya Gokhale,et al.  Automatic Synthesis of Parallel Programs Targeted to Dynamically Reconfigurable Logic Arrays , 1995, FPL.

[25]  A. El Gamal,et al.  Architecture of field-programmable gate arrays , 1993, Proc. IEEE.

[26]  Steven A. Guccione,et al.  Run-time parameterizable cores , 1999, FPGA '99.

[27]  Dionysios I. Reisis,et al.  Parallel Computations on Reconfigurable Meshes , 1993, IEEE Trans. Computers.

[28]  Brad L. Hutchings,et al.  An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing , 1995, FPL.

[29]  Viktor K. Prasanna,et al.  DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems , 1999, FPL.

[30]  Anant Agarwal,et al.  Virtual wires: overcoming pin limitations in FPGA-based logic emulators , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[31]  Stephen M. Scalera,et al.  The design and implementation of a context switching FPGA , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[32]  Sharad Malik,et al.  Solving Boolean Satisfiability with Dynamic Hardware Configurations , 1998, FPL.

[33]  André DeHon,et al.  Reconfigurable architectures for general-purpose computing , 1996 .

[34]  Patrick Lysaght,et al.  A simulation tool for dynamically reconfigurable field programmable gate arrays , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[35]  Harvey F. Silverman,et al.  Processor reconfiguration through instruction-set metamorphosis , 1993, Computer.

[36]  Malgorzata Marek-Sadowska,et al.  Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs , 1999, IEEE Trans. Computers.

[37]  Viktor K. Prasanna,et al.  Fast parallel implementation of DFT using configurable devices , 1997, FPL.

[38]  Viktor K. Prasanna,et al.  High-performance computing for vision , 1996, Proc. IEEE.

[39]  Viktor K. Prasanna,et al.  Modeling and mapping for dynamically reconfigurable hybrid architectures , 2001 .

[40]  William H. Mangione-Smith,et al.  Dynamic circuit generation for solving specific problem instances of Boolean satisfiability , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[41]  Richard J. Carter,et al.  Teramac configurable custom computer , 1995, Optics East.

[42]  Scott Hauck,et al.  The roles of FPGAs in reprogrammable systems , 1998, Proc. IEEE.

[43]  Gordon J. Brebner,et al.  A Virtual Hardware Operating System for the Xilinx XC6200 , 1996, FPL.

[44]  Brad L. Hutchings,et al.  Improving functional density through run-time constant propagation , 1997, FPGA '97.

[45]  Reiner W. Hartenstein,et al.  An operating system for custom computing machines based on the Xputer paradigm , 1997, FPL.

[46]  Dinesh Bhatia,et al.  Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers , 1999, IEEE Trans. Computers.

[47]  John J. Granacki,et al.  DEFACTO: A Design Environment for Adaptive Computing Technology , 1999, IPPS/SPDP Workshops.

[48]  Jonathan Rose,et al.  FPGA and CPLD Architectures: A Tutorial , 1996, IEEE Des. Test Comput..

[49]  Wayne Luk,et al.  Using Reconfigurable Hardware to Speed up Product Development and Performance , 1995, FPL.