Area-Efficient Evaluation of a Class of Arithmetic Expressions Using Deeply Pipelined Floating-Point Cores

Due to technological advances,it has becomepossible to implement floating-point coreson FPGAs in an effort to provide hardware acceleration for the myriad applications that require high performance floating-point arithmetic. However, in order to achieve a high clock rate, these floating-point cores must be deeply pipelined. Due to this deep pipelining and the complexity of floating-point arithmetic, floating-point cores use a great deal of the FPGA’s area. It is thus important to use as few floating-point cores in an architecture as possible.However, the deep pipelining makes it difficult to reusethe samefloatingpoint core for a series of floating-point computations that are dependent upon one another. In this paper, we describe an area-efficient architecture and algorithm for the evaluation of arithmetic expressions.This design effectively hides the pipeline latencyof the floating-point coresand usesonly onefloating-point core for each type of operator in the expression.The design is applicable to a wide variety of fields suchasscientific computing, cognition, and graph theory. We analyzethe performance of this design when implemented on a Xilinx Virtex-II Pro FPGA.