A model-based extensible framework for efficient application design using FPGA
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[1] Nikil D. Dutt,et al. IDAP: a tool for high-level power estimation of custom array structures , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] Viktor K. Prasanna,et al. Rapid design space exploration of heterogeneous embedded systems using symbolic search and multi-granular simulation , 2002, LCTES/SCOPES '02.
[3] Alok N. Choudhary,et al. An algorithm for synthesis of large time-constrained heterogeneous adaptive systems , 2001, TODE.
[4] Ramachandran Vaidyanathan,et al. Adaptive image filtering using run-time reconfiguration , 2003, Proceedings International Parallel and Distributed Processing Symposium.
[5] E.A. Lee,et al. Synchronous data flow , 1987, Proceedings of the IEEE.
[6] Viktor K. Prasanna,et al. A hierarchical approach for energy efficient application design using heterogeneous embedded systems , 2003, CASES '03.
[7] Alex K. Jones,et al. PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations , 2002, CASES '02.
[8] Edward A. Lee,et al. Synthesis of Embedded Software from Synchronous Dataflow Specifications , 1999, J. VLSI Signal Process..
[9] Hans Knutsson,et al. Adaptive image filtering , 2000 .
[10] Gabor Karsai,et al. Model-Integrated Computing , 1997, Computer.
[11] Douglas Samuel Kirk,et al. Defining the problems of framework reuse , 2002, Proceedings 26th Annual International Computer Software and Applications.
[12] Viktor K. Prasanna,et al. Domain-Specific Modeling for Rapid System-Wide Energy Estimation of Reconfigurable Architectures , 2002 .
[13] Li Shang,et al. High-level power modeling of CPLDs and FPGAs , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.
[14] Luca Benini,et al. A survey of design techniques for system-level dynamic power management , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[15] Viktor K. Prasanna,et al. On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication , 1991, IEEE Trans. Computers.
[16] Viktor K. Prasanna,et al. Energy-Efficient Matrix Multiplication on FPGAs , 2002, FPL.
[17] Viktor K. Prasanna,et al. Performance modeling of reconfigurable SoC architectures and energy-efficient mapping of a class of application , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..
[18] Viktor K. Prasanna,et al. Energy-efficient and parameterized designs for fast Fourier transform on FPGAs , 2003, 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03)..
[19] Majid Sarrafzadeh,et al. A C to hardware/software compiler , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).
[20] L. Almagor,et al. Finding effective compilation sequences , 2004, LCTES '04.
[21] Frank Vahid,et al. A quantitative analysis of the speedup factors of FPGAs over processors , 2004, FPGA '04.
[22] Sandeep K. Shukla,et al. An environment for dynamic component composition for efficient co-design , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[23] David Robinson,et al. A Hardwar/Software Co-design Environment for Reconfigurable Logic Systems , 1998, FPL.
[24] Sandeep Neema,et al. Modeling methodology for integrated simulation of embedded systems , 2003, TOMC.
[25] Viktor K. Prasanna,et al. An Algorithm Designer's Workbench for Platform FPGA's , 2003, FPL.
[26] Seda Ogrenci Memik,et al. Power-Driven Design Partitioning , 2004, FPL.
[27] Wayne Luk,et al. Automating production of run-time reconfigurable designs , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).
[28] Eike Schmidt,et al. System level optimization and design space exploration for low power , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).
[29] Viktor K. Prasanna,et al. Loop Pipelining and Optimization for Run Time Reconfiguration , 2000, IPDPS Workshops.
[30] Viktor K. Prasanna,et al. Domain-Specific Modeling for Rapid Energy Estimation of Reconfigurable Architectures , 2004, The Journal of Supercomputing.
[31] Fadi J. Kurdahi,et al. A framework for reconfigurable computing: task scheduling and context management , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[32] Paul Frank Singer. Optimal detector , 2002, SPIE Defense + Commercial Sensing.
[33] K PrasannaViktor,et al. A model-based extensible framework for efficient application design using FPGA , 2007 .
[34] Majid Sarrafzadeh,et al. An optimal algorithm for minimizing run-time reconfiguration delay , 2004, TECS.