Energy optimization of parallel k-means clustering algorithm on FPGA

The k-means clustering algorithm is commonly used to partition a set of input vectors into k clusters where the member vectors have the minimum distance to each cluster center. Depending on the input dataset, computation time of k-means clustering can be significant. In the past, many methods have been developed for minimizing the overall processing time of k-means clustering. In recent years, energy efficiency is becoming an increasingly important design requirement. In this work, we propose a parallel and parametrized k-means clustering architecture on FPGA. Using the parameterized architecture, we develop algorithmic optimizations to improve energy efficiency with minimal effect on the computation throughput including a memory and logic activation schedule. In addition, we investigate the power and performance scalability of k-means clustering on FPGA. When compared against state-of-the-art designs, our optimized architecture consumes only 14.7% of the energy consumed by the state-of-the-art design and achieves up to 4× higher energy efficiency when compared against the baseline architecture.