Reduce Register Files Leakage Through Discharging Cells

We propose a low-leakage register file cell design based on the observation that the physical registers in a superscalar processor have very short life cycles. When a register is dead, we discharge its cells to '0' to greatly reduce the leakage current from the read bitlines to the ground. Our design has no impact to critical register read access path. Projected to future 45 nm technology, our design yields additional 38% and 47% leakage power savings on top of the existing low-leakage cell designs for 64-bit and 32-bit datapath, respectively. Taking into the account of dynamic energy savings due to the elimination of write '0' operations, our design saves nearly 20% of total energy.

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