Parallel Algorithms and Architectures for Consistent Labeling

Publisher Summary This chapter describes parallel algorithms and architectures for consistent labeling. The chapter presents the development of a simple systolic implementation of the straightforward sequential method and of a faster sequential algorithm that runs in O ( n 2 m 2 ) time. In the latter algorithm, each time unit corresponds to a simple arithmetic/logic operation. Based on this algorithm, a second design is proposed. The designs assume that a communication step takes comparable time as a computation step. A parallel algorithm to handle this situation is also presented in the chapter. This algorithm is suitable for implementation on distributed and shared memory multiprocessor systems. Results of implementation of this algorithm on various configurations of an iPSC/860 are also presented in the chapter.