The First 25 Years of the FPL Conference

A summary of contributions made by significant papers from the first 25 years of the Field-Programmable Logic and Applications conference (FPL) is presented. The 27 papers chosen represent those which have most strongly influenced theory and practice in the field.

[1]  Vaughn Betz,et al.  Bringing programmability to the data plane: Packet processing with a NoC-enhanced FPGA , 2015, 2015 International Conference on Field Programmable Technology (FPT).

[2]  Jeff Mason,et al.  Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[3]  Marco Platzner,et al.  Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks , 2004, IEEE Transactions on Computers.

[4]  John Kelsey,et al.  Status Report on the Second Round of the SHA-3 Cryptographic Hash Algorithm Competition , 2011 .

[5]  Dionisios N. Pnevmatikatos,et al.  Fast, Large-Scale String Match for a 10Gbps FPGA-Based Network Intrusion Detection System , 2003, FPL.

[6]  Stylianos Perissakis,et al.  Stream computations organized for reconfigurable execution , 2006, Microprocess. Microsystems.

[7]  Chao Yang,et al.  Accelerating solvers for global atmospheric equations through mixed-precision data flow engine , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[8]  Ron K. Cytron,et al.  A Scalable Architecture For High-Throughput Regular-Expression Pattern Matching , 2006, ISCA 2006.

[9]  Lars Braun,et al.  Data reallocation by exploiting FPGA configuration mechanisms , 2008, ARC.

[10]  Jürgen Teich,et al.  DyNoC: A dynamic infrastructure for communication in dynamically reconfugurable devices , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[11]  Mahmut T. Kandemir,et al.  A Dual-VDD Low Power FPGA Architecture , 2004, FPL.

[12]  Marco Platzner,et al.  Significant papers from the first 25 years of the FPL conference , 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

[13]  Jason Helge Anderson,et al.  Active leakage power optimization for FPGAs , 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Marco Platzner,et al.  ReconOS: Multithreaded programming for reconfigurable computers , 2009, TECS.

[15]  Jürgen Teich,et al.  A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[16]  Tsutomu Maruyama,et al.  Performance comparison of FPGA, GPU and CPU in image processing , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[17]  Markus Weinhardt,et al.  PACT XPP—A Self-Reconfigurable Data Processing Architecture , 2004, The Journal of Supercomputing.

[18]  Edusmildo Orozco,et al.  Reconfigurable Computing. Accelerating Computation with Field-Programmable Gate Arrays , 2007, Scalable Comput. Pract. Exp..

[19]  Wayne Luk,et al.  SONIC - A Plug-In Architecture for Video Processing , 1999, FPL.

[20]  Vaughn Betz,et al.  The power of communication: Energy-efficient NOCS for FPGAS , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[21]  Ron K. Cytron,et al.  A Scalable Architecture For High-Throughput Regular-Expression Pattern Matching , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[22]  Martin C. Herbordt,et al.  Families of FPGA-based accelerators for approximate string matching , 2007, Microprocess. Microsystems.

[23]  Bertil Schmidt,et al.  Reconfigurable architectures for bio-sequence database scanning on FPGAs , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[24]  Martin Straka,et al.  Fault tolerant system design and SEU injection based testing , 2013, Microprocess. Microsystems.

[25]  David M. Lewis,et al.  Architectural enhancements in Stratix V™ , 2013, FPGA '13.

[26]  Reiner W. Hartenstein,et al.  Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing , 2002, Lecture Notes in Computer Science.

[27]  Patrick Crowley,et al.  Algorithms to accelerate multiple regular expressions matching for deep packet inspection , 2006, SIGCOMM 2006.

[28]  Morris J. Dworkin,et al.  SHA-3 Standard: Permutation-Based Hash and Extendable-Output Functions , 2015 .

[29]  Jason Cong,et al.  Power modeling and characteristics of field programmable gate arrays , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[30]  Marco Platzner,et al.  Virtualizing Hardware with Multi-context Reconfigurable Arrays , 2003, FPL.

[31]  Michael R. Butts,et al.  A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable Computing , 2007 .

[32]  S. D. Haynes,et al.  UltraSONIC: A Reconfigurable Architecture for Video Image Processing , 2002, FPL.

[33]  Uwe Meyer-Baese.  Digital Signal Processing with Field Programmable Gate Arrays , 2001 .

[34]  Wenhai Li,et al.  A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor , 2013, FCCM 2013.

[35]  Reinhard Männer,et al.  Multitasking on FPGA Coprocessors , 2000, FPL.

[36]  Jürgen Teich,et al.  ReCoBus-Builder — A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[37]  Vaughn Betz,et al.  VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.

[38]  Mario Konijnenburg,et al.  ULP-SRP: Ultra low power Samsung Reconfigurable Processor for biomedical applications , 2012, 2012 International Conference on Field-Programmable Technology.

[39]  Timothy Sherwood,et al.  A high throughput string matching architecture for intrusion detection and prevention , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

[40]  Ingrid Verbauwhede,et al.  Physically Unclonable Functions: A Study on the State of the Art and Future Research Directions , 2010, Towards Hardware-Intrinsic Security.

[41]  Stamatis Vassiliadis,et al.  Regular Expression Matching in Reconfigurable Hardware , 2008, J. Signal Process. Syst..

[42]  Jürgen Becker,et al.  An FPGA run-time system for dynamical on-demand reconfiguration , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[43]  Steven J. E. Wilton,et al.  A Flexible Power Model for FPGAs , 2002, FPL.

[44]  Jim Tørresen,et al.  Go Ahead: A Partial Reconfiguration Framework , 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines.

[45]  Wayne Luk,et al.  The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays , 2004, FPL.

[46]  Michael J. Flynn,et al.  StReAm: object-oriented programming of stream architectures using PAM-Blox , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

[47]  John Dunlop,et al.  Dynamic reconfiguration of FPGAs , 1994 .

[48]  Wayne Luk,et al.  Architectures and Precision Analysis for Modelling Atmospheric Variables with Chaotic Behaviour , 2015, 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines.

[49]  William P. Marnane,et al.  FPGA Implementations of the Round Two SHA-3 Candidates , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[50]  Philip Heng Wai Leong,et al.  A Smith-Waterman Systolic Cell , 2003, FPL.

[51]  Sen Wang,et al.  VTR 7.0: Next Generation Architecture and CAD System for FPGAs , 2014, TRETS.

[52]  Gordon J. Brebner,et al.  A Virtual Hardware Operating System for the Xilinx XC6200 , 1996, FPL.

[53]  Vaughn Betz,et al.  Take the Highway: Design for Embedded NoCs on FPGAs , 2015, FPGA.

[54]  Rudy Lauwereins,et al.  Networks on Chip as Hardware Components of an OS for Reconfigurable Systems , 2003, FPL.

[55]  Michael J. Wirthlin,et al.  FPGA Bootstrapping on PCIe Using Partial Reconfiguration , 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

[56]  Dionisios N. Pnevmatikatos,et al.  Pre-decoded CAMs for efficient and high-speed NIDS pattern matching , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[57]  Rudy Lauwereins,et al.  ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix , 2003, FPL.

[58]  Christopher R. Clark,et al.  Scalable pattern matching for high speed networks , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[59]  Natalie D. Enright Jerger,et al.  Efficient and programmable ethernet switching with a NoC-enhanced FPGA , 2014, 2014 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS).

[60]  Vaughn Betz,et al.  Efficient and Deterministic Parallel Placement for FPGAs , 2011, TODE.

[61]  Carl Ebeling,et al.  RaPiD - Reconfigurable Pipelined Datapath , 1996, FPL.

[62]  Heiko Kalte,et al.  Context saving and restoring for multitasking in reconfigurable systems , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[63]  Koen Bertels,et al.  The Instruction-Set Extension Problem: A Survey , 2008, TRETS.

[64]  Fernando Gehm Moraes,et al.  HERMES: an infrastructure for low area overhead packet-switching networks on chip , 2004, Integr..

[65]  Michael J. Flynn,et al.  Beyond Traditional Microprocessors for Geoscience High-Performance Computing Applications , 2011, IEEE Micro.

[66]  Eduardo Ros,et al.  A Comparison of FPGA and GPU for Real-Time Phase-Based Optical Flow, Stereo, and Local Image Features , 2012, IEEE Transactions on Computers.

[67]  Peter D. Düben,et al.  Benchmark Tests for Numerical Weather Forecasts on Inexact Hardware , 2014 .

[68]  G.-J. Schrijen,et al.  Physical Unclonable Functions and Public-Key Crypto for FPGA IP Protection , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[69]  Maya Gokhale,et al.  Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays , 2005 .

[70]  Michael J. Wirthlin,et al.  FPGA partial reconfiguration via configuration scrubbing , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[71]  Steve Poole,et al.  Granidt: Towards Gigabit Rate Network Intrusion Detection Technology , 2002, FPL.

[72]  Nachiket Kapre,et al.  VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration , 2011, 2011 International Conference on Field-Programmable Technology.

[73]  Brad L. Hutchings,et al.  An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing , 1995, FPL.

[74]  PlatznerMarco,et al.  The First 25 Years of the FPL Conference , 2017 .

[75]  John Wawrzynek,et al.  Stream Computations Organized for Reconfigurable Execution (SCORE) , 2000, FPL.

[76]  Joshua S. Auerbach,et al.  Lime: a Java-compatible and synthesizable language for heterogeneous architectures , 2010, OOPSLA.