An Intelligent Lossless Data Compressor Implementation using Reconfigurable Hardware

Reconfigurable computing is emerging as the new area for satisfying the simultaneous demand for application performance and flexibility. The ability to customize the architecture to match the computation and the data flow of the application has demonstrated significant performance benefits compared to general purpose architectures. In signal processing, multimedia, high speed communication are the major application domains that have significant heterogeneity in their computation and communication structure with various advantages. The reconfigurability of the hardware permits adaptation of the hardware for specific computations in each application to achieve higher performance compared to software. Complex functions can be mapped onto the architecture achieving higher silicon utilization and reducing the instruction fetch and execute bottleneck. In this paper we proposed and implemented a high speed CODEC (for Lossless Compression) which compress the real time image for high speed communication..

[1]  Jer Min Jou,et al.  Dynamic pipeline design of an adaptive binary arithmetic coder , 2001 .

[2]  Mark Nelson,et al.  The Data Compression Book , 1991 .

[3]  R. Nigel Horspool,et al.  Data Compression Using Dynamic Markov Modelling , 1987, Comput. J..

[4]  Amit Konar,et al.  CAM based high-speed compressed data communication system development using FPGA , 2009, 2009 World Congress on Nature & Biologically Inspired Computing (NaBIC).

[5]  Viktor K. Prasanna,et al.  Seeking Solutions in Configurable Computing , 1997, Computer.

[6]  Ian H. Witten,et al.  Data Compression Using Adaptive Coding and Partial String Matching , 1984, IEEE Trans. Commun..

[7]  Brad Hutchings,et al.  The flexibility of configurable computing , 1998 .

[8]  J. D. Bruguera,et al.  A VLSI architecture for arithmetic coding of multilevel images , 1998 .

[9]  Scott Hauck,et al.  The roles of FPGAs in reprogrammable systems , 1998, Proc. IEEE.

[10]  David A. Huffman,et al.  A method for the construction of minimum-redundancy codes , 1952, Proceedings of the IRE.

[11]  Amit Konar,et al.  High-Speed Communication System Development Using FPGA Based CAM Implementation , 2009, 2009 Second International Conference on Emerging Trends in Engineering & Technology.

[12]  G. Blelloch Introduction to Data Compression * , 2022 .

[13]  Abraham Lempel,et al.  A universal algorithm for sequential data compression , 1977, IEEE Trans. Inf. Theory.

[14]  Alistair Moffat,et al.  Implementing the PPM data compression scheme , 1990, IEEE Trans. Commun..