Loop Pipelining and Optimization for Run Time Reconfiguration

Lack of automatic mapping techniques is a significant hurdle in obtaining high performance for general purpose computing on reconfigurable hardware. In this paper, we develop techniques for mapping loop computations from applications onto high performance pipelined configurations. Loop statements with generalized directed acyclic graph dependencies are mapped onto multiple pipeline segments. Each pipeline segment is executed for a fixed number of iterations before the hardware is reconfigured at runtime to execute the next segment. The reconfiguration cost is amortized over the multiple iterations of the execution of the loop statements. This alleviates the bottleneck of high reconfiguration overheads in current architectures. The paper describes heuristic techniques to construct pipeline configurations which have reduced total execution time including the runtime reconfiguration overheads. The performance benefits which can be achieved using our approach are illustrated by mapping example application loop onto Virtex series FPGA from Xilinx.