A Note on the Linear Transformation Method for Systolic Array Design

The use of the linear transformation method to systolize the Warshall algorithm for computing the transitive closure of a graph on a mesh-connected array (without wraparound connections) is discussed. The technique is extended to design linear systolic arrays. The advantage of this approach is easy verification of correctness, as well as synthesis of a family of arrays with tradeoffs between I/O bandwidth, number of processing elements, and local storage. The technique can be further refined to cope with problems that entail nonconstant dependency vectors. >

[1]  Sun-Yuan Kung,et al.  Optimal Systolic Design for the Transitive Closure and the Shortest Path Problems , 1987, IEEE Transactions on Computers.

[2]  Viktor K. Prasanna,et al.  On Mapping Algorithms to Linear and Fault-Tolerant Systolic Arrays , 1989, IEEE Trans. Computers.

[3]  H. T. Kung,et al.  Direct VLSI Implementation of Combinatorial Algorithms , 1979 .

[4]  Robert H. Kuhn.  Efficient mapping of algorithms to single-stage interconnections , 1980, ISCA '80.

[5]  Peter R. Cappello,et al.  Unifying VLSI Array Designs with Geometric Transformations , 1983, International Conference on Parallel Processing.

[6]  Benjamin W. Wah,et al.  Systematic approaches to the design of algorithmically specified systolic arrays , 1985, ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing.

[7]  Carla D. Savage.  A Systolic Data Structure Chip for Connectivity Problems , 1981 .

[8]  Frances L. Van Scoy.  The Parallel Recognition of Classes of Graphs , 1980, IEEE Trans. Computers.

[9]  H. T. Kung,et al.  Systolic Arrays for (VLSI). , 1978 .

[10]  Leslie Lamport,et al.  The parallel execution of DO loops , 1974, CACM.

[11]  I. V. Ramakrishnan,et al.  Synthesis of an Optimal Family of Matrix Multiplication Algorithms on Linear Arrays , 1986, IEEE Transactions on Computers.

[12]  I. V. Ramakrishnan,et al.  Dynamic Programming and Transitive Closure on Linear Pipelines. , 1984 .

[13]  Rami G. Melhem,et al.  The application of a sequence notation to the design of systolic computations , 1989, BIT.

[14]  Pradip K. Srimani,et al.  A Parallel Algorithm to Compute the Shortest Paths and Diameter of a Graph and Its VLSI Implementation , 1986, IEEE Transactions on Computers.

[15]  I. V. Ramakrishnan,et al.  Optimal Matrix Multiplication on Fault-Tolerant VLSI Arrays , 1989, IEEE Trans. Computers.

[16]  Sailesh K. Rao,et al.  Regular interactive algorithms and their implementations on processor arrays , 1986 .

[17]  D.I. Moldovan,et al.  On the design of algorithms for VLSI systolic arrays , 1983, Proceedings of the IEEE.

[18]  H. T. Kung,et al.  Wafer-scale integration and two-level pipelined implementations of systolic arrays , 1984, J. Parallel Distributed Comput..

[19]  Rami G. Melhem,et al.  Synthesizing Non-Uniform Systolic Designs , 1986, ICPP.

[20]  Richard M. Karp,et al.  The Organization of Computations for Uniform Recurrence Equations , 1967, JACM.

[21]  H. Kung,et al.  An algebra for VLSI algorithm design , 1983 .

[22]  Dan I. Moldovan,et al.  On the Analysis and Synthesis of VLSI Algorithms , 1982, IEEE Transactions on Computers.

[23]  Marina C. Chen,et al.  A Design Methodology for Synthesizing Parallel Algorithms and Architectures , 1986, J. Parallel Distributed Comput..

[24]  Alfred V. Aho,et al.  The Design and Analysis of Computer Algorithms , 1974 .