Blind identification of power sources in processors

The ability to measure power consumption is at the heart of power and thermal management techniques. Modern processors are equipped with hardware monitoring mechanisms that can measure total power. However, this lumped measurement is not sufficient if there is a need to execute fine-grain thermal and power management techniques. This paper proposes a new direction for identifying the fine-grain sources of power consumption in many-core processors. For the first time, we show that it is possible to simultaneously identify both the power consumption of different cores and the thermal model of the chip from just the measurements of the thermal sensors and the total power consumption measurement. Our identification technique is blind as it does not require design knowledge of the thermal model to identify the power sources. Furthermore, our technique makes no use of the performance counters, which reduces its overhead, and works seamlessly with dynamic voltage and frequency scaling. We implement our technique on a real multi-core CPU-GPU processor-based system, and we show the ability to identify the runtime power consumption of the individual cores using just the total power measurement and the measurements of the thermal sensors under different workloads. We also verify the superior accuracy of our approach using results from a controlled simulation environment.

[1]  Eric Moulines,et al.  A blind source separation technique using second-order statistics , 1997, IEEE Trans. Signal Process..

[2]  H. Sebastian Seung,et al.  Learning the parts of objects by non-negative matrix factorization , 1999, Nature.

[3]  Tajana Simunic,et al.  Accurate Temperature Estimation for Efficient Thermal Management , 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

[4]  Kai Ma,et al.  Temperature-constrained power control for chip multiprocessors with online model estimation , 2009, ISCA '09.

[5]  Rahul Khanna,et al.  RAPL: Memory power estimation and capping , 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

[6]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[7]  Sherief Reda,et al.  Post-silicon power characterization using thermal infrared emissions , 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

[8]  Tajana Simunic,et al.  Utilizing Predictors for Efficient Thermal Management in Multiprocessor SoCs , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Kevin Skadron,et al.  HotSpot: a compact thermal modeling methodology for early-stage VLSI design , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Margaret Martonosi,et al.  Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power Management , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[11]  Luca Benini,et al.  Static Thermal Model Learning for High-Performance Multicore Servers , 2011, 2011 Proceedings of 20th International Conference on Computer Communications and Networks (ICCCN).

[12]  Sherief Reda,et al.  Consistent runtime thermal prediction and control through workload phase detection , 2010, Design Automation Conference.

[13]  Sheldon X.-D. Tan,et al.  Parameterized architecture-level dynamic thermal models for multicore microprocessors , 2010, TODE.

[14]  Luca Benini,et al.  An Effective Gray-Box Identification Procedure for Multicore Thermal Modeling , 2014, IEEE Transactions on Computers.

[15]  Luca Benini,et al.  A distributed and self-calibrating model-predictive controller for energy and thermal management of high-performance multicores , 2011, 2011 Design, Automation & Test in Europe.

[16]  Aapo Hyvärinen,et al.  Fast and robust fixed-point algorithms for independent component analysis , 1999, IEEE Trans. Neural Networks.

[17]  Joseph Shor,et al.  A Fully Integrated Multi-CPU, Processor Graphics, and Memory Controller 32-nm Processor , 2012, IEEE Journal of Solid-State Circuits.