A Library of Parameterizable Floating-Point Cores for FPGAs and Their Application to Scientific Computing

Advances in field programmable gate arrays (FPGAs), which are the platform of choice for reconfigurable computing, have made it possible to use FPGAs in increasingly ma ny areas of computing, including complex scientific applicati ons. These applications demand high performance and high-preci s on, floating-point arithmetic. Until now, most of the research has not focussed on compliance with IEEE standard 754, focusing ins tead upon custom formats and bitwidths. In this paper, we present double-precision floating-point cores that are parameteri zed by their degree of pipelining and the features of IEEE standard754 that they implement. We then analyze the effects of supporti ng the standard when these cores are used in an FPGA-based accelerator for Lennard-Jones force and potential calculations that are part of molecular dynamics (MD) simulations.

[1]  John F. Wakerly,et al.  Digital design - principles and practices , 1990, Prentice Hall Series in computer engineering.

[2]  Karl S. Hemmert,et al.  Closing the gap: CPU and FPGA trends in sustainable floating-point BLAS performance , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[3]  Yamin Li,et al.  A new non-restoring square root algorithm and its VLSI implementations , 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

[4]  Viktor K. Prasanna,et al.  Efficient Floating-point Based Block LU Decomposition on FPGAs , 2004, ERSA.

[5]  E J Yoder.  DESIGN PRINCIPLES AND PRACTICES - CONCRETE PAVEMENTS , 1979 .

[6]  Scott McMillan,et al.  A re-evaluation of the practicality of floating-point operations on FPGAs , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[7]  Nick Tredennick,et al.  Reconfigurable Systems Emerge , 2004, FPL.

[8]  Viktor K. Prasanna,et al.  Analysis of high-performance floating-point arithmetic on FPGAs , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[9]  Viktor K. Prasanna,et al.  Scalable and modular algorithms for floating-point matrix multiplication on FPGAs , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[10]  Barry S. Fagin,et al.  Field programmable gate arrays and floating point arithmetic , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Keith D. Underwood,et al.  FPGAs vs. CPUs: trends in peak floating-point performance , 2004, FPGA '04.

[12]  J. Banavar,et al.  Computer Simulation of Liquids , 1988 .

[13]  Viktor K. Prasanna,et al.  Computing Lennard-Jones Potentials and Forces with Reconfigurable Hardware , 2004, ERSA.

[14]  Guido D. Salvucci,et al.  Ieee standard for binary floating-point arithmetic , 1985 .

[15]  Pavle Belanovic,et al.  A Library of Parameterized Floating-Point Modules and Their Use , 2002, FPL.

[16]  Arnaud Tisserand,et al.  Reciprocation, square root, inverse square root, and some elementary functions using small multipliers , 1998, Optics & Photonics.

[17]  Russell Tessier,et al.  Floating point unit generation and evaluation for FPGAs , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..

[18]  Todd A. Cook,et al.  Implementation of IEEE single precision floating point addition and multiplication on FPGAs , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[19]  Reinhard Männer,et al.  Using floating-point arithmetic on FPGAs to accelerate scientific N-Body simulations , 2002, Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.