Algorithmic optimizations for energy efficient throughput-oriented FFT architectures on FPGA

Energy efficiency is a key design metric when implementing signal processing applications on FPGAs. In this paper, high level energy optimizations are proposed to facilitate the development of an energy efficient throughput-oriented FFT design. At the algorithm mapping level, we develop a data remapping technique and a memory activation scheduling method to reduce memory energy consumption. At the architecture binding level, we explore and identify the optimal memory binding scheme and pipelining strategy of the floating point units. The experimental results show that the dynamic power dissipation is reduced significantly using the proposed algorithmic optimizations. Compared with the baseline architecture, the optimized architecture achieves 2.97x, 2.99x and 3.05x improvement in energy-efficiency (defined as GFLOPS/W) for 256, 4096 and 32768 point FFTs, respectively. Compared with the state-of-the-art designs, our implementation realizes up to 7.39x energy efficiency improvement while sustaining almost 20x throughput (defined as MPoints/s) performance.