DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems

Current simulation tools for reconfigurable systems are based on low level simulation of application designs developed in a High-level Description Language(HDL) on HDL models of architectures. This necessitates expertise on behalf of the user to generate the low level design before performance analysis can be accomplished. Most of the current simulation tools also are based on static designs and do not support analysis of dynamic reconfiguration.

[1]  Reiner W. Hartenstein,et al.  An operating system for custom computing machines based on the Xputer paradigm , 1997, FPL.

[2]  Andreas Koch Unified access to heterogeneous module generators , 1999, FPGA '99.

[3]  Viktor K. Prasanna,et al.  Mapping Loops onto Reconfigurable Architectures , 1998, FPL.

[4]  W. Luk,et al.  Visualising reconfigurable libraries for FPGAs , 1997, Conference Record of the Thirty-First Asilomar Conference on Signals, Systems and Computers (Cat. No.97CB36136).

[5]  John Wawrzynek,et al.  Object oriented circuit-generators in Java , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[6]  Patrick Lysaght,et al.  A simulation tool for dynamically reconfigurable field programmable gate arrays , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[7]  Michael J. Flynn,et al.  PAM-Blox: high performance FPGA design for adaptive computing , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[8]  Viktor K. Prasanna,et al.  Dynamic precision management for loop computations on reconfigurable architectures , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[9]  Wayne Luk,et al.  Visualising Recon gurable Libraries for FPGAs , 1997 .

[10]  Wayne Luk,et al.  Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research , 1997, FPL.

[11]  John J. Granacki,et al.  DEFACTO: A Design Environment for Adaptive Computing Technology , 1999, IPPS/SPDP Workshops.

[12]  Brad L. Hutchings,et al.  JHDL-an HDL for reconfigurable systems , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[13]  Steven A. Guccione,et al.  Run-time parameterizable cores , 1999, FPGA '99.