H. Wong

发表

On the Switching Parameter Variation of Metal Oxide RRAM—Part II: Model Corroboration and Device Design Strategy

Shimeng Yu, X. Guan, H. Wong, 2012, IEEE Transactions on Electron Devices.

H. Wong, Zhiping Zhang, Yi Wu, 2013 .

On the stochastic nature of resistive switching in metal oxide RRAM: Physical modeling, monte carlo simulation, and experimental characterization

Shimeng Yu, X. Guan, H. Wong, 2011, 2011 International Electron Devices Meeting.

Design Considerations for Complementary Nanoelectromechanical Logic Gates

R. Howe, H. Wong, K. Akarvardar, 2007, 2007 IEEE International Electron Devices Meeting.

Three-dimensional "atomistic" simulation of discrete random dopant distribution effects in sub-0.1 /spl mu/m MOSFET's

H. Wong, Y. Taur, 1993, Proceedings of IEEE International Electron Devices Meeting.

An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory

H. Wong, Y. Nishi, H. Jagannathan, 2007, 2007 IEEE Symposium on VLSI Technology.

Carbon nanotube field effect transistors for logic applications

H. Wong, P. Avouris, R. Martel, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Monolithic integration of CMOS VLSI and CNT for hybrid nanotechnology applications

H. Wong, D. Akinwande, S. Yasuda, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region

H. Wong, Jie Deng, 2007, IEEE Transactions on Electron Devices.

Read/write schemes analysis for novel complementary resistive switches in passive crossbar memory arrays.

Shimeng Yu, H. Wong, Yi Wu, 2010, Nanotechnology.

Modeling and Analysis of Planar-Gate Electrostatic Capacitance of 1-D FET With Multiple Cylindrical Conducting Channels

H. Wong, Jie Deng, 2007, IEEE Transactions on Electron Devices.

Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes

H. Wong, S. Mitra, Chongwu Zhou, 2009, IEEE Transactions on Nanotechnology.

Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits

H. Wong, S. Mitra, N. Patil, 2009, IEEE Transactions on Nanotechnology.

CMOS scaling into the nanometer regime

H. Wong, D. Frank, S. Wind, 1997, Proc. IEEE.

A Circuit-Compatible SPICE model for Enhancement Mode Carbon Nanotube Field Effect Transistors

H. Wong, J. Deng, 2006, 2006 International Conference on Simulation of Semiconductor Processes and Devices.

Generalized Phase Change Memory Scaling Rule Analysis

H. Wong, Sangbum Kim, 2006, 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop.

Phase change nanodot arrays fabricated using a self-assembly diblock copolymer approach

H. Wong, C. Rettner, T. Topuria, 2007 .

Biomimetic Approaches for Fabricating High-Density Nanopatterned Arrays

H. Wong, C. Rettner, S. Raoux, 2007 .

Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique

H.-S. Philip Wong, Subhasish Mitra, Chen Chen, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Integration of nanoelectromechanical (NEM) relays with silicon CMOS with functional CMOS-NEM circuit

R. Howe, H. Wong, S. Mitra, 2011, 2011 International Electron Devices Meeting.

Nanoelectromechanical Logic and Memory Devices

H. Wong, K. Akarvardar, 2009 .

COMPOSITE POLYSILICON-PLATINUM LATERAL NANOELECTROMECHANICAL RELAYS

R. Howe, H. Wong, S. Mitra, 2010 .

On the Switching Parameter Variation of Metal-Oxide RRAM—Part I: Physical Modeling and Simulation Methodology

Shimeng Yu, X. Guan, H. Wong, 2012, IEEE Transactions on Electron Devices.

Energy-Efficient Abundant-Data Computing: The N3XT 1,000x

Kunle Olukotun, Franz Franchetti, Jan M. Rabaey, 2015, Computer.

Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs

Tony F. Wu, K. Saraswat, H. Wong, 2014, 2014 IEEE International Electron Devices Meeting.

VLSI-compatible carbon nanotube doping technique with low work-function metal oxides.

H. Wong, Z. Bao, G. Pitner, 2014, Nano letters.

3D vertical RRAM - Scaling limit analysis and demonstration of 3D array operation

Shimeng Yu, H. Wong, Jinfeng Kang, 2013, 2013 Symposium on VLSI Technology.

Investigating the switching dynamics and multilevel capability of bipolar metal oxide resistive switching memory

Shimeng Yu, H. Wong, Yi Wu, 2011 .

A neuromorphic visual system using RRAM synaptic devices with Sub-pJ energy and tolerance to variability: Experimental characterization and large-scale modeling

Shimeng Yu, H. Wong, Jinfeng Kang, 2012, 2012 International Electron Devices Meeting.

A SPICE Compact Model of Metal Oxide Resistive Switching Memory With Variations

Shimeng Yu, X. Guan, H. Wong, 2012, IEEE Electron Device Letters.

Parasitic Capacitances: Analytical Models and Impact on Circuit-Level Performance

H. Wong, T. Skotnicki, F. Boeuf, 2011, IEEE Transactions on Electron Devices.

Integrated wafer-scale growth and transfer of directional Carbon Nanotubes and misaligned-Carbon-Nanotube-immune logic structures

H. Wong, S. Mitra, N. Patil, 2008, 2008 Symposium on VLSI Technology.

A 1TnR array architecture using a one-dimensional selection device

H. Wong, Jiale Liang, Chi-Shuen Lee, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Large‐Area Assembly of Densely Aligned Single‐Walled Carbon Nanotubes Using Solution Shearing and Their Application to Field‐Effect Transistors

Ja Hoon Koo, H. Wong, Zhenan Bao, 2015, Advanced materials.

Experimental demonstration of high mobility Ge NMOS

K. Saraswat, H. Wong, A. Nainani, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Electrostatic analysis of carbon nanotube arrays

H. Wong, P. Oldiges, Xinlin Wang, 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..

Synaptic electronics: materials, devices and applications

Shimeng Yu, H. Wong, H. Philip Wong, 2013, Nanotechnology.

Effect of annealing ambient and temperature on the electrical characteristics of atomic layer deposition Al2O3/In0.53Ga0.47As metal-oxide-semiconductor capacitors and MOSFETs

H. Wong, Jenny Hu, 2012 .

Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI

Francky Catthoor, H.-S. Philip Wong, Iuliana Radu, 2018, IEEE Transactions on Nanotechnology.

Carbon nanomaterials for non-volatile memories

Ethan C. Ahn, H. Wong, E. Pop, 2018 .

Modeling of schottky and ohmic contacts between metal and graphene nanoribbons using extended hückel theory (EHT)-based NEGF method

Zhiping Yu, Ximeng Guan, X. Guan, 2008, 2008 IEEE International Electron Devices Meeting.

Nanoscale Bipolar and Complementary Resistive Switching Memory Based on Amorphous Carbon

Shimeng Yu, Ali Javey, Hong-Yu Chen, 2011, IEEE Transactions on Electron Devices.

Integrating Phase-Change Memory Cell With Ge Nanowire Diode for Crosspoint Memory—Experimental Demonstration and Analysis

Y. Nishi, Yuan Zhang, H. Jagannathan, 2008, IEEE Transactions on Electron Devices.

Forming-free nitrogen-doped AlOX RRAM with sub-μA programming current

H. Wong, Zhiping Zhang, S. Wong, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Fabrication and Characterization of Nanoscale NiO Resistance Change Memory (RRAM) Cells With Confined Conduction Paths

Byoungil Lee, H. Wong, Byoungil Lee, 2011, IEEE Transactions on Electron Devices.

A Phenomenological Model for the Reset Mechanism of Metal Oxide RRAM

Shimeng Yu, H. Wong, 2010, IEEE Electron Device Letters.

Conduction mechanism of TiN/HfOx/Pt resistive switching memory: A trap-assisted-tunneling model

Shimeng Yu, X. Guan, H. Wong, 2011 .

A Monte Carlo study of the low resistance state retention of HfOx based resistive switching memory

Shimeng Yu, X. Guan, H. Wong, 2012 .

Analysis of the Frequency Response of Carbon Nanotube Transistors

H. Wong, D. Akinwande, G. Close, 2006, IEEE Transactions on Nanotechnology.

Uniaxial Stress Engineering for High-Performance Ge NMOSFETs

K. Saraswat, H. Wong, Y. Nishi, 2010, IEEE Transactions on Electron Devices.

Investigation of the performance limits of III-V double-gate n-MOSFETs

K. Saraswat, H. Wong, Y. Nishi, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Carbon Nanotube And Graphene Device Physics

H. Wong, D. Akinwande, 2010 .

AlOx-Based Resistive Switching Device with Gradual Resistance Modulation for Neuromorphic Device Application

Shimeng Yu, M. Tsai, H. Wong, 2012, 2012 4th IEEE International Memory Workshop.

Cost-effective, transfer-free, flexible resistive random access memory using laser-scribed reduced graphene oxide patterning technology.

H. Wong, Yezhou Yang, T. Ren, 2014, Nano letters.

Atomically thin graphene plane electrode for 3D RRAM

H. Wong, Hong-Yu Chen, Zizhen Jiang, 2014, 2014 IEEE International Electron Devices Meeting.

Monitoring oxygen movement by Raman spectroscopy of resistive random access memory with a graphene-inserted electrode.

Shimeng Yu, H. Wong, Jinfeng Kang, 2013, Nano letters.

Flexible Control of Block Copolymer Directed Self‐Assembly using Small, Topographical Templates: Potential Lithography Solution for Integrated Circuit Contact Hole Patterning

H. Wong, S. Mitra, Li-Wen Chang, 2012, Advanced materials.

Ultralow Voltage Crossbar Nonvolatile Memory Based on Energy-Reversible NEM Switches

H. Wong, K. Akarvardar, 2009, IEEE Electron Device Letters.

Nanoelectromechanical relays with decoupled electrode and suspension

R. Howe, H. Wong, R. Parsa, 2011, 2011 IEEE 24th International Conference on Micro Electro Mechanical Systems.

Electrical and mechanical characterization of lateral NEMS Switches

R. Howe, H. Wong, K. Akarvardar, 2011, 2011 Symposium on Design, Test, Integration & Packaging of MEMS/MOEMS (DTIP).

Integration of Nanoelectromechanical Relays With Silicon nMOS

R. Howe, H. Wong, S. Mitra, 2012, IEEE Transactions on Electron Devices.

Partitioning Electrostatic and Mechanical Domains in Nanoelectromechanical Relays

R. Howe, H. Wong, S. Mitra, 2015, Journal of Microelectromechanical Systems.

Laterally Actuated Platinum-Coated Polysilicon NEM Relays

R. Howe, H. Wong, S. Mitra, 2013, Journal of microelectromechanical systems.

Unipolar n-Type Black Phosphorus Transistors with Low Work Function Contacts.

H. Wong, E. Pop, J. Incorvia, 2018, Nano letters.

Laterally actuated nanoelectromechanical relays with compliant, low resistance contact

R. Howe, H. Wong, S. Mitra, 2013, 2013 IEEE 26th International Conference on Micro Electro Mechanical Systems (MEMS).

HfOx-based vertical resistive switching random access memory suitable for bit-cost-effective three-dimensional cross-point architecture.

Shimeng Yu, H. Wong, Jinfeng Kang, 2013, ACS nano.

Ultrathin (∼2nm) HfOx as the fundamental resistive switching element: Thickness scaling limit, stack engineering and 3D integration

H. Wong, Y. Nishi, Liang Zhao, 2014, 2014 IEEE International Electron Devices Meeting.

A phenomenological model of oxygen ion transport for metal oxide resistive switching memory

Shimeng Yu, H. Wong, 2010, 2010 IEEE International Memory Workshop.

Verilog-A compact model for oxide-based resistive random access memory (RRAM)

Shimeng Yu, X. Guan, H. Wong, 2014, 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

Next-Generation Ultrahigh-Density 3-D Vertical Resistive Switching Memory (VRSM)—Part I: Accurate and Computationally Efficient Modeling

H. Wong, S. Wong, Zizhen Jiang, 2019, IEEE Transactions on Electron Devices.

Carbon Nanotube Transistor Circuits - Models and Tools for Design and Performance Optimization

H. Wong, G. Wan, T. Krishnamohan, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

MoS2 transistors with 1-nanometer gate lengths

Moon J. Kim, H. Wong, C. Hu, 2016, Science.

Impact of a Process Variation on Nanowire and Nanotube Device Performance

H. Wong, Y. Nishi, B. Paul, 2007, IEEE Transactions on Electron Devices.

Characterization of switching parameters and multilevel capability in HfOx/AlOx bi-layer RRAM devices

Shimeng Yu, H. Wong, Yi Wu, 2011, Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications.

Exceeding Nernst limit (59mV/pH): CMOS-based pH sensor for autonomous applications

H. Wong, A. Poon, K. B. Parizi, 2012, 2012 International Electron Devices Meeting.

An Analytical Derivation of the Density of States, Effective Mass, and Carrier Density for Achiral Carbon Nanotubes

H. Wong, Y. Nishi, D. Akinwande, 2008, IEEE Transactions on Electron Devices.

A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part II: Extrinsic Elements, Performance Assessment, and Design Optimization

H. Wong, E. Pop, W. Haensch, 2015, IEEE Transactions on Electron Devices.

$\hbox{Al}_{2}\hbox{O}_{3}$-Based RRAM Using Atomic Layer Deposition (ALD) With 1-$\mu\hbox{A}$ RESET Current

H. Wong, Yi Wu, Byoungil Lee, 2010, IEEE Electron Device Letters.

Crystallization times of Ge–Te phase change materials as a function of composition

H. Wong, S. Raoux, Huai-Yu Cheng, 2009 .

Computing with Carbon Nanotubes

H. Wong, S. Mitra, M. Shulaker, 2016, IEEE Spectrum.

Analytical ballistic theory of carbon nanotube transistors: Experimental validation, device physics, parameter extraction, and performance projection

H. Wong, Y. Nishi, D. Akinwande, 2008 .

A metallic-CNT-tolerant carbon nanotube technology using Asymmetrically-Correlated CNTs (ACCNT)

Hai Wei, S. Mitra, N. Patil, 2006, 2009 Symposium on VLSI Technology.

Schottky-Barrier Carbon Nanotube Field-Effect Transistor Modeling

H. Wong, H.-S.P. Wong, T. Krishnamohan, 2007, IEEE Transactions on Electron Devices.

Measuring Frequency Response of a Single-Walled Carbon Nanotube Common-Source Amplifier

I. Amlani, H. Wong, I. Amlani, 2009, IEEE Transactions on Nanotechnology.

Air-stable technique for fabricating n-type carbon nanotube FETs

Hai Wei, H.-S. Philip Wong, Subhasish Mitra, 2011, 2011 International Electron Devices Meeting.

Electrode/oxide interface engineering by inserting single-layer graphene: Application for HfOx-based resistive random access memory

Shimeng Yu, He Tian, Tian-Ling Ren, 2012, 2012 International Electron Devices Meeting.

A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors.

Shinobu Fujita, Shinichi Yasuda, H. Wong, 2008, Nano letters.

In situ transmission electron microscopy observation of nanostructural changes in phase-change memory.

H.-S. Philip Wong, Stefan Meister, SangBum Kim, 2011, ACS nano.

Efficient metallic carbon nanotube removal readily scalable to wafer-level VLSI CNFET circuits

Hai Wei, Jie Zhang, Subhasish Mitra, 2010, 2010 Symposium on VLSI Technology.

5. Phase Change Memory

Ethan C. Ahn, H. Wong, R. Jeyasingh, 2014 .

Microthermal Stage for Electrothermal Characterization of Phase-Change Memory

H. Wong, Sangbum Kim, M. Asheghi, 2011, IEEE Electron Device Letters.

Investigation of Trap Spacing for the Amorphous State of Phase-Change Memory Devices

H. Wong, D. Kuzum, R. Jeyasingh, 2011, IEEE Transactions on Electron Devices.

Thermal Boundary Resistance Measurements for Phase-Change Memory Devices

M. Asheghi, Sangbum Kim, H. Wong, 2010, IEEE Electron Device Letters.

Measurement of anisotropy in the thermal conductivity of Ge2Sb2Te5 films

H. Wong, Sangbum Kim, M. Asheghi, 2009, 2009 10th Annual Non-Volatile Memory Technology Symposium (NVMTS).

Wafer Bonding for High-Performance Logic Applications

Kathryn W. Guarini, H. Wong, K. Guarini, 2004 .

Synthesis and Size-Dependent Crystallization of Colloidal Germanium Telluride

H.-S. Philip Wong, Simone Raoux, Delia J. Milliron, 2010 .

Scaling properties of phase change materials

Yuan Zhang, S. Raoux, H. Wong, 2007, 2007 Non-Volatile Memory Technology Symposium.

One-Dimensional Thickness Scaling Study of Phase Change Material $(\hbox{Ge}_{2}\hbox{Sb}_{2}\hbox{Te}_{5})$ Using a Pseudo 3-Terminal Device

In-Gyu Baek, Seok-Woo Nam, SangBum Kim, 2011, IEEE Transactions on Electron Devices.

Low frequency noise in phase change materials

H.-S. Philip Wong, Gerard Ghibaudo, Mireille Mouis, 2011, 2011 21st International Conference on Noise and Fluctuations.

Vertical and Lateral Copper Transport through Graphene Layers.

Ji Cao, Michael S Arnold, Seunghyun Lee, 2015, ACS nano.

Nanometer-Scale ${\rm HfO}_{x}$ RRAM

H.-S. Philip Wong, H. Wong, Zhiping Zhang, 2013, IEEE Electron Device Letters.

Assembly and Electrical Characterization of Multiwall Carbon Nanotube Interconnects

H. Wong, G. Close, H.-S.P. Wong, 2008, IEEE Transactions on Nanotechnology.

Sub-ns Delay Through Multi-Wall Carbon Nanotube Local Interconnects in a CMOS Integrated Circuit

H. Wong, S. Yasuda, B. Paul, 2008, 2008 International Interconnect Technology Conference.

Fabrication and Characterization of Carbon Nanotube Interconnects

H. Wong, G. Close, Helen Wong, 2007, 2007 IEEE International Electron Devices Meeting.

Carbon Nanotubes for Monolithic 3D ICs

H. Wong, S. Mitra, M. Shulaker, 2017 .

Compact Model for Carbon Nanotube Field-Effect Transistors Including Nonidealities and Calibrated With Experimental Data Down to 9-nm Gate Length

D. A. Antoniadis, Ximeng Guan, Jieying Luo, 2013, IEEE Transactions on Electron Devices.

Statistical Study on the Schottky Barrier Reduction of Tunneling Contacts to CVD Synthesized MoS2.

Seunghyun Lee, H. Wong, S. Aloni, 2016, Nano letters.

High-Mobility Ge N-MOSFETs and Mobility Degradation Mechanisms

Duygu Kuzum, Aneesh Nainani, Tejas Krishnamohan, 2011, IEEE Transactions on Electron Devices.

SiGe-on-insulator prepared by wafer bonding and layer transfer for high-performance field-effect transistors

H.-S. Philip Wong, Steven J. Koester, Jack O. Chu, 2001 .

Current Scaling in Aligned Carbon Nanotube Array Transistors With Local Bottom Gating

Albert Lin, Zhihong Chen, H. Wong, 2010, IEEE Electron Device Letters.

A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part I: Intrinsic Elements

H. Wong, E. Pop, W. Haensch, 2015, IEEE Transactions on Electron Devices.

Variability in carbon nanotube transistors: improving device-to-device consistency.

Davood Shahrjerdi, Wilfried Haensch, Hong-Yu Chen, 2012, ACS nano.

Statistical study of RRAM MLC SET variability induced by filament morphology

H. Wong, Yi Wu, Chung-Wei Hsu, 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

3-D Cross-Point Array Operation on ${\rm AlO}_{y}/{\rm HfO}_{x}$ -Based Vertical Resistive Switching Memory

Shimeng Yu, Jinfeng Kang, Rui Liu, 2014, IEEE Transactions on Electron Devices.

Integrating Graphene into Future Generations of Interconnect Wires

H. Wong, Ling Li, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Localized Triggering of the Insulator-Metal Transition in VO2 Using a Single Carbon Nanotube.

H. Wong, E. Pop, S. Parkin, 2019, ACS nano.

All-Metal-Nitride RRAM Devices

G. Lo, H. Wong, Zhiping Zhang, 2015, IEEE Electron Device Letters.

Beyond the conventional transistor

H.-S. Philip Wong, H. Wong, 2002, IBM J. Res. Dev..

A 1.4µA reset current phase change memory cell with integrated carbon nanotube electrodes for cross-point memory application

Jiale Liang, Rakesh Gnana David Jeyasingh, Hong-Yu Chen, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Fully Integrated Graphene and Carbon Nanotube Interconnects for Gigahertz High-Speed CMOS Electronics

Jing Kong, Kyeong-Jae Lee, H. Wong, 2010, IEEE Transactions on Electron Devices.

Cross plane thermal conductance of graphene-metal interfaces

H. Wong, Y. Nishi, M. Asheghi, 2014, Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm).

Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections

H.-S. Philip Wong, Jie Deng, Nishant Patil, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Imperfection-Immune Carbon Nanotube VLSI Circuits

H. Wong, S. Mitra, N. Patil, 2011 .

Fault-Tolerant Circuit for Carbon Nanotube Transistors with Si-CMOS Hybrid Circuitry

H. Wong, D. Akinwande, S. Yasuda, 2008, 2008 8th IEEE Conference on Nanotechnology.

Titanium nitride sidewall stringer process for lateral nanoelectromechanical relays

S. Mitra, J. Provine, R. Howe, 2010, 2010 IEEE 23rd International Conference on Micro Electro Mechanical Systems (MEMS).

2D molybdenum disulfide (MoS2) transistors driving RRAMs with 1T1R configuration

Eric Pop, Kirby K. H. Smithe, H.-S. Philip Wong, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Gate-current injection and surface impact ionization in MOSFET's with a gate induced virtual drain

H. Wong, 1992, 1992 International Technical Digest on Electron Devices Meeting.

Characterization of phase-change layer thermal properties using a micro-thermal stage

H. Wong, M. Asheghi, K. Goodson, 2014, Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems.

Phonon and electron transport through Ge2Sb2Te5 films and interfaces bounded by metals

H. Wong, Sangbum Kim, M. Asheghi, 2013 .

Molybdenum oxide on carbon nanotube: Doping stability and correlation with work function

H. Wong, S. Mitra, G. Pitner, 2020 .

Illusion of large on-chip memory by networked computing chips for neural network inference

Tony F. Wu, Zainab F. Khan, E. Vianello, 2021, Nature Electronics.

Ultrafast characterization of phase-change material crystallization properties in the melt-quenched amorphous phase.

Mehdi Asheghi, Jaeho Lee, Rakesh Jeyasingh, 2014, Nano letters.

Atomic layer deposition of high-k dielectrics on single-walled carbon nanotubes: a Raman study

H. Wong, Zhenan Bao, S. Van Elshocht, 2013, Nanotechnology.

Electrical properties of CuPc-based OTFTs with atomic layer deposited HfAlO gate dielectric

R. Howe, H. Wong, J. Provine, 2012, 2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC).

Monolithic III–V nanowire PV for photoelectrochemical hydrogen generation

H. Wong, T. Jaramillo, S. Aloni, 2010, 2010 35th IEEE Photovoltaic Specialists Conference.

Graphene Interconnect Lifetime: A Reliability Analysis

D. Seo, H. Wong, Hyun-Jong Chung, 2012, IEEE Electron Device Letters.

Intrinsic limits of leakage current in self-heating-triggered threshold switches

R. Williams, H. Wong, Y. Nishi, 2019, Applied Physics Letters.

Effect of thermal insulation on the electrical characteristics of NbOx threshold switches

H. Wong, Y. Nishi, Suhas Kumar, 2018 .

Electro-Thermal Confinement Enables Improved Superlattice Phase Change Memory

Asir Intisar Khan, H. Wong, E. Pop, 2022, IEEE Electron Device Letters.

AC stress and electronic effects on SET switching of HfO2 RRAM

H. Wong, T. Hou, Xin Zheng, 2017 .

Ultra-Low Power Ni/HfO2/TiOx/TiN Resistive Random Access Memory With Sub-30-nA Reset Current

Fang Wang, Zizhen Jiang, Kailiang Zhang, 2015, IEEE Electron Device Letters.

CMOS scaling into the 21st century: 0.1 µm and beyond

Yuan Taur, H.-S. Philip Wong, David J. Frank, 1995, IBM J. Res. Dev..

Templated DSA vias in sub-7 nm circuits: Design strategy and DSA-aware via decomposition

Geert Vandenberghe, H.-S. Philip Wong, Wim Dehaene, 2016 .

Metal-induced dopant (boron and phosphorus) activation process in amorphous germanium for monolithic three-dimensional integration

H.-S. Philip Wong, Krishna C. Saraswat, Munehiro Tada, 2009 .

Impact of fixed charge on metal-insulator-semiconductor barrier height reduction

H.-S. Philip Wong, Krishna C. Saraswat, Aneesh Nainani, 2011 .

High Current Density and Low Thermal Conductivity of Atomically Thin Semimetallic WTe2.

H. Wong, E. Pop, Y. Nishi, 2016, ACS nano.

Nanoscale phase change memory materials.

H. Wong, D. Milliron, M. Caldwell, 2012, Nanoscale.

Synthesis of metal chalcogenide nanodot arrays using block copolymer-derived nanoreactors.

H. Wong, D. Milliron, M. Caldwell, 2007, Nano letters.

Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution.

H. Wong, S. Mitra, G. Hills, 2016, ACS nano.

Advancements with carbon nanotube digital systems

H. Wong, S. Mitra, N. Patil, 2014, IEEE International Interconnect Technology Conference.

Nanoscale science and technology - a device and engineering perspective

H. Wong, 2003, 2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668).

AC characterization of top-gated carbon nanotube field effect transistors

H. Wong, K. Jenkins, J. Appenzeller, 2003, International Semiconductor Device Research Symposium, 2003.

Electronic synapses made of layered two-dimensional materials

Eric Pop, H.-S. Philip Wong, Mario Lanza, 2018, Nature Electronics.

Coexistence of volatile and non-volatile resistive switching in 2D h-BN based electronic synapses

H. Wong, E. Pop, M. Lanza, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Improved gradual resistive switching range and 1000× on/off ratio in HfOx RRAM achieved with a Ge2Sb2Te5 thermal barrier

K. Saraswat, H. Wong, E. Pop, 2022, Applied Physics Letters.

Novel graphene-based devices

H. Wong, T. Ren, H. Tian, 2013, 2013 IEEE International Conference of Electron Devices and Solid-state Circuits.

A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part I: Intrinsic Elements

H. Wong, E. Pop, W. Haensch, 2015, IEEE Transactions on Electron Devices.

Picosecond Electric-Field-Induced Threshold Switching in Phase-Change Materials.

Matthias Wuttig, Meng-Ju Sher, Peter Jost, 2016, Physical review letters.

Coming Up N3XT, After 2D Scaling of Si CMOS

H.-S. Philip Wong, Weier Wan, Subhasish Mitra, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.

Subhasish Mitra, Albert Lin, Chongwu Zhou, 2009, Nano letters.

Efficient FPGAs using nanoelectromechanical relays

H.-S. Philip Wong, Nishant Patil, Subhasish Mitra, 2010, FPGA '10.

Electronic and optical switching of solution-phase deposited SnSe2 phase change memory material

H. Wong, R. Shelby, D. Milliron, 2011 .

Distinctive in-Plane Cleavage Behaviors of Two-Dimensional Layered Materials.

Junfeng Dai, Haimin Yao, Yang Chai, 2016, ACS nano.

Phase-Change Memory—Towards a Storage-Class Memory

H.-S. Philip Wong, Scott W. Fong, Christopher M. Neumann, 2017, IEEE Transactions on Electron Devices.

Synaptic Devices Based on Phase-Change Memory

H.-S. Philip Wong, Yuhan Shi, Duygu Kuzum, 2017 .

Spatial Separation of Carrier Spin by the Valley Hall Effect in Monolayer WSe2 Transistors.

Eric Pop, H. Wong, E. Pop, 2019, Nano letters.

Understanding the switching mechanism of interfacial phase change memory

Eric Pop, Eilam Yalon, H.-S. Philip Wong, 2019, Journal of Applied Physics.

Digital VLSI logic technology using Carbon Nanotube FETs: Frequently Asked Questions

H.-S. Philip Wong, Nishant Patil, Subhasish Mitra, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Modeling Carbon Nanotube Sensors

H. Wong, Jie Deng, K. Ghosh, 2007, IEEE Sensors Journal.

An Electronic Synapse Device Based on Metal Oxide Resistive Switching Memory for Neuromorphic Computation

Shimeng Yu, H. P. Wong, Yi Wu, 2011, IEEE Transactions on Electron Devices.

Carbon nanotube computer

H.-S. Philip Wong, Subhasish Mitra, Gage Hills, 2013, Nature.

Monolithic Integration of CMOS VLSI and Carbon Nanotubes for Hybrid Nanotechnology Applications

S. Fujita, D. Akinwande, S. Yasuda, 2008, IEEE Transactions on Nanotechnology.

Cu diffusion barrier: Graphene benchmarked to TaN for ultimate interconnect scaling

Michael S. Arnold, Ji Cao, Susmit Singha Roy, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

A Density Metric for Semiconductor Technology [Point of View]

H.-S. Philip Wong, Jeffrey Bokor, James D. Plummer, 2020, Proc. IEEE.

Face classification using electronic synapses

H.-S. Philip Wong, Luping Shi, Wenqiang Zhang, 2017, Nature Communications.

Fermi-level depinning in metal/Ge Schottky junction and its application to metal source/drain Ge NMOSFET

Y. Nishi, A. Kinoshita, K. Saraswat, 2008, 2008 Symposium on VLSI Technology.

Improved Performance of Bottom-Contact Organic Thin-Film Transistor Using Al Doped HfO2 Gate Dielectric

Roger T. Howe, J. Provine, R. Howe, 2014, IEEE Transactions on Electron Devices.

Carbon nanotube circuit integration up to sub-20 nm channel lengths.

Hai Wei, Eric Pop, Georges Gielen, 2014, ACS nano.

Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs

Hai Wei, Georges G. E. Gielen, H.-S. Philip Wong, 2014, IEEE Journal of Solid-State Circuits.

Increasing the semiconducting fraction in ensembles of single-walled carbon nanotubes

H.-S. Philip Wong, Albert Lin, Hong-Yu Chen, 2012 .

Selective synthesis and device applications of semiconducting single-walled carbon nanotubes using isopropyl alcohol as feedstock.

Chongwu Zhou, Yuchi Che, H. Wong, 2012, ACS nano.

Wafer-scale fabrication and characterization of thin-film transistors with polythiophene-sorted semiconducting carbon nanotube networks.

Zhenan Bao, Subhasish Mitra, Nishant Patil, 2012, ACS nano.

Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations

H.-S. Philip Wong, Nishant Patil, Subhasish Mitra, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Effect of Wordline/Bitline Scaling on the Performance, Energy Consumption, and Reliability of Cross-Point Memory Array

H.-S. Philip Wong, S. Simon Wong, Jiale Liang, 2013, JETC.

Resistive switching random access memory — Materials, device, interconnects, and scaling considerations

Shimeng Yu, Ximeng Guan, Jiale Liang, 2012, 2012 IEEE International Integrated Reliability Workshop Final Report.

Scaling Challenges for the Cross-Point Resistive Memory Array to Sub-10nm Node - An Interconnect Perspective

Jiale Liang, S. Yeh, S. S. Wong, 2012, 2012 4th IEEE International Memory Workshop.

Size limitation of cross-point memory array and its dependence on data storage pattern and device parameters

H.-S. Philip Wong, Jiale Liang, H. Wong, 2010, 2010 IEEE International Interconnect Technology Conference.

Fabrication and characterization of emerging nanoscale memory

Yuan Zhang, H.-S. Philip Wong, Byoungil Lee, 2009, 2009 IEEE International Symposium on Circuits and Systems.

An Ultra-Low Reset Current Cross-Point Phase Change Memory With Carbon Nanotube Electrodes

Jiale Liang, Hong-Yu Chen, R. G. D. Jeyasingh, 2012, IEEE Transactions on Electron Devices.

Low-voltage high-performance flexible digital and analog circuits based on ultrahigh-purity semiconducting carbon nanotubes

H. Wong, K. Cheng, Zhenan Bao, 2019, Nature Communications.

The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance

T. Skotnicki, H.-S.P. Wong, F. Boeuf, 2005, IEEE Circuits and Devices Magazine.

Artificial optic-neural synapse for colored and color-mixed pattern recognition

H. Wong, D. Kuzum, Jin-Hong Park, 2018, Nature Communications.

Special session paper 3D nanosystems enable embedded abundant-data computing

H.-S. Philip Wong, Christos Kozyrakis, Mingyu Gao, 2017, 2017 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Nanoelectronic programmable synapses based on phase change materials for brain-inspired computing.

Byoungil Lee, Duygu Kuzum, Rakesh G D Jeyasingh, 2012, Nano letters.

Heterogeneous 3D Nano-systems: The N3XT Approach?

H.-S. Philip Wong, Subhasish Mitra, Mohamed M. Sabry Aly, 2020 .

Ternary content-addressable memory with MoS2 transistors for massively parallel data search

Eric Pop, Kirby K. H. Smithe, H.-S. Philip Wong, 2019, Nature Electronics.

Four-layer 3D vertical RRAM integrated with FinFET as a versatile computing unit for brain-inspired cognitive information processing

S. Burc Eryilmaz, Min-Cheng Chen, Jia-Min Shieh, 2016, 2016 IEEE Symposium on VLSI Technology.

Design and optimization methodology for 3D RRAM arrays

Shimeng Yu, Bing Chen, Jinfeng Kang, 2013, 2013 IEEE International Electron Devices Meeting.

HfOx based vertical resistive random access memory for cost-effective 3D cross-point architecture without cell selector

Shimeng Yu, Peng Huang, Jinfeng Kang, 2012, 2012 International Electron Devices Meeting.

Resistive RAM-Centric Computing: Design and Modeling Methodology

H.-S. Philip Wong, Subhasish Mitra, Haitong Li, 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators

H.-S. Philip Wong, Paul N. Whatmough, Mudit Bhargava, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array

Chung Lam, H.-S. Philip Wong, Sukru Burc Eryilmaz, 2014, Front. Neurosci..

Experimental demonstration of array-level learning with phase change synaptic devices

Chung Lam, H.-S. Philip Wong, Sukru Burc Eryilmaz, 2013, 2013 IEEE International Electron Devices Meeting.

Optoelectronic resistive random access memory for neuromorphic vision sensors

Shimeng Yu, Jinfeng Kang, H-S Philip Wong, 2019, Nature Nanotechnology.

Ultra-low-energy three-dimensional oxide-based electronic synapses for implementation of robust high-accuracy neuromorphic computation systems.

Shimeng Yu, Bing Chen, Peng Huang, 2014, ACS nano.

Carbon Nanotube Robust Digital VLSI

Hai Wei, H.-S. Philip Wong, Lan Wei, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Noniterative Compact Modeling for Intrinsic Carbon-Nanotube FETs: Quantum Capacitance and Ballistic Transport

D. J. Frank, H. Wong, D. Frank, 2011, IEEE Transactions on Electron Devices.

ACCNT: A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Analyses and Design Guidelines

Hai Wei, Jie Zhang, H.-S Philip Wong, 2010, IEEE Transactions on Electron Devices.

Carbon Nanotube Device Modeling and Circuit Simulation

H.-S. Philip Wong, Jie Deng, Albert Lin, 2009 .

Carbon nanotube transistor compact model for circuit design and performance optimization

H.-S. Philip Wong, Jie Deng, Albert Lin, 2008, JETC.

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking

Jie Deng, H.-S.P. Wong, H. Wong, 2007, IEEE Transactions on Electron Devices.

Schottky-Barrier Carbon Nanotube Field Effect Transistor Modeling

Arash Hazeghi, Tejas Krishnamohan, H. Wong, 2006 .

Removable and Recyclable Conjugated Polymers for Highly Selective and High-Yield Dispersion and Release of Low-Cost Carbon Nanotubes.

H.-S. Philip Wong, Xiyuan Chen, Zhenan Bao, 2016, Journal of the American Chemical Society.

Energy-Efficient Phase-Change Memory with Graphene as a Thermal Barrier.

Eric Pop, Mehdi Asheghi, Seunghyun Lee, 2015, Nano letters.

Stochastic learning in oxide binary synaptic device for neuromorphic computing

Shimeng Yu, H.-S. Philip Wong, Zheng Fang, 2013, Front. Neurosci..

In Situ Tuning of Switching Window in a Gate‐Controlled Bilayer Graphene‐Electrode Resistive Memory Device

He Tian, Mohammad Ali Mohammad, Tian-Ling Ren, 2015, Advanced materials.

Metal–Oxide RRAM

Shimeng Yu, H.-S. Philip Wong, Heng-Yuan Lee, 2012, Proceedings of the IEEE.

Two-Fold Reduction of Switching Current Density in Phase Change Memory Using Bi₂Te₃ Thermoelectric Interfacial Layer

Asir Intisar Khan, H. Wong, E. Pop, 2020, IEEE Electron Device Letters.

Measurability Issues in the Radio-Frequency Characterization of Carbon Nanotubes

H. Wong, G. Close, 2006, 2006 Sixth IEEE Conference on Nanotechnology.

Finite element analysis and analytical simulations of Suspended Gate-FET for ultra-low power inverters

Adrian M. Ionescu, H.-S. Philip Wong, Yogesh Singh Chauhan, 2008 .

Phase Change Memory

H.-S. Philip Wong, Simone Raoux, Mehdi Asheghi, 2010, Proceedings of the IEEE.

High-Performance p-Type Black Phosphorus Transistor with Scandium Contact.

M. Engel, H. Wong, D. Farmer, 2016, ACS nano.

Universal Selective Dispersion of Semiconducting Carbon Nanotubes from Commercial Sources Using a Supramolecular Polymer.

H. Wong, Zhenan Bao, Alex Chortos, 2017, ACS nano.

Single-Tube Characterization Methodology for Experimental and Analytical Evaluation of Carbon Nanotube Synthesis

Hai Wei, Subhasish Mitra, Albert Lin, 2011 .

Analytical Modeling of the Suspended-Gate FET and Design Insights for Low-Power Logic

H.-S.P. Wong, A.M. Ionescu, K. Akarvardar, 2008, IEEE Transactions on Electron Devices.

Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies

Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

Metrics for performance benchmarking of nanoscale Si and carbon nanotube FETs including device nonidealities

H. Wong, Jie Deng, H.-S.P. Wong, 2006, IEEE Transactions on Electron Devices.

Performance Estimation and Benchmarking for Carbon Nanotube FETs and Nanodiode Arrays

Gary S. Ditlow, H.-S. Philip Wong, Paul M. Solomon, 2003 .

The Impact of Device Footprint Scaling on High-Performance CMOS Logic Technology

Ching-Te Chuang, Keunwoo Kim, Jie Deng, 2007, IEEE Transactions on Electron Devices.

Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI

Ching-Te Chuang, H.-S. Philip Wong, Keunwoo Kim, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Write disturb analyses on half-selected cells of cross-point RRAM arrays

Shimeng Yu, Bing Chen, Peng Huang, 2014, 2014 IEEE International Reliability Physics Symposium.

Device-architecture co-design for hyperdimensional computing with 3d vertical resistive switching random access memory (3D VRRAM)

H.-S. Philip Wong, Subhasish Mitra, Haitong Li, 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Metal/III-V Schottky barrier height tuning for the design of nonalloyed III-V field-effect transistor source/drain contacts

H.-S. Philip Wong, Krishna C. Saraswat, Jenny Hu, 2010 .

Fermi level depinning in metal/Ge Schottky junction for metal source/drain Ge metal-oxide-semiconductor field-effect-transistor application

K. Saraswat, H. Wong, Y. Nishi, 2009 .

Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations

Hai Wei, H.-S. Philip Wong, Subhasish Mitra, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Robust design and experimental demonstrations of carbon nanotube digital circuits

Hai Wei, H.-S. Philip Wong, Subhasish Mitra, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

Rapid exploration of processing and design guidelines to overcome carbon nanotube variations

Hai Wei, H.-S. Philip Wong, Subhasish Mitra, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact model

D. Chidambarrao, H. Wong, S. Laux, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Efficient metallic carbon nanotube removal for highly-scaled technologies

Zhenan Bao, Subhasish Mitra, Gage Hills, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

A Voltage-Mode Sensing Scheme with Differential-Row Weight Mapping For Energy-Efficient RRAM-Based In-Memory Computing

Gert Cauwenberghs, Weier Wan, Rajkumar Kubendran, 2020, 2020 IEEE Symposium on VLSI Technology.

Decoupled thermal resistances of phase change material and their impact on PCM devices

H. Wong, Sangbum Kim, M. Asheghi, 2010, 2010 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems.

Thickness and stoichiometry dependence of the thermal conductivity of GeSbTe films

Eric Pop, H.-S. Philip Wong, Kenneth E. Goodson, 2007 .

Fast Spiking of a Mott VO2-Carbon Nanotube Composite Device.

Eric Pop, R. Stanley Williams, Stuart S. P. Parkin, 2019, Nano letters.

Phase Change Memory: Scaling and applications

H.-S. Philip Wong, Jiale Liang, Duygu Kuzum, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

A Physics-Based Compact Model for CBRAM Retention Behaviors Based on Atom Transport Dynamics and Percolation Theory

H.-S. Philip Wong, Jinfeng Kang, Lifeng Liu, 2019, IEEE Electron Device Letters.

The Role of Ti Capping Layer in HfOx-Based RRAM Devices

Guo-Qiang Lo, Dim-Lee Kwong, Zheng Fang, 2014, IEEE Electron Device Letters.

Characterization of low-frequency noise in the resistive switching of transition metal oxide HfO 2

Shimeng Yu, H.-S. Philip Wong, Rakesh Jeyasingh, 2012 .

Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study

Jan M. Rabaey, H.-S. Philip Wong, Abbas Rahimi, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Transient dynamics of NbOx threshold switches explained by Poole-Frenkel based thermal feedback mechanism

H.-S. Philip Wong, Yoshio Nishi, Suhas Kumar, 2018 .

A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part II: Extrinsic Elements, Performance Assessment, and Design Optimization

H. Wong, E. Pop, W. Haensch, 2015, IEEE Transactions on Electron Devices.

Linear increases in carbon nanotube density through multiple transfer technique.

Hai Wei, Subhasish Mitra, Hong-Yu Chen, 2011, Nano letters.

Carbon Nanotube and Graphene Device Physics: Carbon nanotubes

H.-S. Philip Wong, Deji Akinwande, H. Wong, 2010 .

A general design strategy for block copolymer directed self-assembly patterning of integrated circuits contact holes using an alphabet approach.

Richard Tiberio, H. Wong, X. Bao, 2015, Nano letters.

Analytical approximation of complex band structures for band-to-band tunneling models

K. Saraswat, X. Guan, H. Wong, 2011, 2011 International Conference on Simulation of Semiconductor Processes and Devices.

Complex Band Structures: From Parabolic to Elliptic Approximation

K. Saraswat, X. Guan, H. Wong, 2011, IEEE Electron Device Letters.

Dispersion of High‐Purity Semiconducting Arc‐Discharged Carbon Nanotubes Using Backbone Engineered Diketopyrrolopyrrole (DPP)‐Based Polymers

Zhenan Bao, Xiyuan Chen, Guosong Hong, 2016 .

Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits

Geert Vandenberghe, H.-S. Philip Wong, Wim Dehaene, 2016 .

Block copolymer directed self-assembly enables sublithographic patterning for device fabrication

H.-S. Philip Wong, He Yi, Chris Bencher, 2012, Advanced Lithography.

33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models

Gert Cauwenberghs, Wenqiang Zhang, Weier Wan, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

An integrated capacitance bridge for high-resolution, wide temperature range quantum capacitance measurements.

H. Wong, D. Goldhaber-Gordon, J. Sulpizio, 2010, The Review of scientific instruments.

Layout optimization and template pattern verification for directed self-assembly (DSA)

H.-S. Philip Wong, Zigang Xiao, He Yi, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Directed Self-Assembly (DSA) Template Pattern Verification

Yuelin Du, H.-S. Philip Wong, Zigang Xiao, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Low-Resistance Electrical Contact to Carbon Nanotubes With Graphitic Interfacial Layer

Hong-Yu Chen, Yang Chai, K. Takei, 2012, IEEE Transactions on Electron Devices.

Ultrafast Accelerated Retention Test Methodology for RRAM Using Micro Thermal Stage

H.-S. Philip Wong, Yoshio Nishi, Hong-Yu Chen, 2017, IEEE Electron Device Letters.

Hyperdimensional Computing Nanosystem pdf

Jan M. Rabaey, H.-S. Philip Wong, Abbas Rahimi, 2018, ArXiv.

Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration

Jan M. Rabaey, H.-S. Philip Wong, Abbas Rahimi, 2018, IEEE Journal of Solid-State Circuits.

Disturbance characteristics of half-selected cells in a cross-point resistive switching memory array

Shimeng Yu, Jinfeng Kang, Rui Liu, 2016, Nanotechnology.

RRAM based synaptic devices for neuromorphic visual systems

Shimeng Yu, H.-S. Philip Wong, Peng Huang, 2015, 2015 IEEE International Conference on Digital Signal Processing (DSP).

Statistical assessment methodology for the design and optimization of cross-point RRAM arrays

Shimeng Yu, Bing Chen, Peng Huang, 2014, 2014 IEEE 6th International Memory Workshop (IMW).

Impact of pulse rise time on programming of cross-point RRAM arrays

Shimeng Yu, Bing Chen, Peng Huang, 2014, Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

First demonstration of RRAM patterned by block copolymer self-assembly

Zizhen Jiang, Joon Sohn, Simon Wong, 2013, 2013 IEEE International Electron Devices Meeting.

On the Variability of HfOx RRAM: From Numerical Simulation to Compact Modeling

Shimeng Yu, H.-S. Philip Wong, Ximeng Guan, 2012 .

Hyperdimensional computing nanosystem: in-memory computing using monolithic 3D integration of RRAM and CNFET

Jan M. Rabaey, H.-S. Philip Wong, Subhasish Mitra, 2020 .

High-performance carbon nanotube field-effect transistors

Subhasish Mitra, Gage Hills, Max M. Shulaker, 2014, 2014 IEEE International Electron Devices Meeting.

Beyond-Silicon Devices: Considerations for Circuits and Architectures

H.-S. Philip Wong, Subhasish Mitra, Gage Hills, 2018, Beyond-CMOS Technologies for Next Generation Computer Design.

Monolithic three-dimensional integration of carbon nanotube FETs with silicon CMOS

Subhasish Mitra, Max M. Shulaker, Krishna Saraswat, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs

Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Carbon nanotube correlation: Promising opportunity for CNFET circuit yield enhancement

Giovanni De Micheli, H.-S. Philip Wong, Nishant Patil, 2010, Design Automation Conference.

VMR: VLSI-compatible metallic carbon nanotube removal for imperfection-immune cascaded multi-stage digital logic circuits using Carbon Nanotube FETs

Hai Wei, Jie Zhang, Subhasish Mitra, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

ACCNT—A Metallic-CNT-Tolerant Design Methodology for Carbon-Nanotube VLSI: Concepts and Experimental Demonstration

Hai Wei, H.-S.P. Wong, S. Mitra, 2009, IEEE Transactions on Electron Devices.

Bandgap Extraction at 10 K to Enable Leakage Control in Carbon Nanotube MOSFETs

H. Wong, S. Mitra, G. Pitner, 2022, IEEE Electron Device Letters.

Extended Scale Length Theory Targeting Low-Dimensional FETs for Carbon Nanotube FET Digital Logic Design-Technology Co-optimization

H. Wong, J. Ryckaert, G. Hellings, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

Scaling Theory of Two-Dimensional Field Effect Transistors

H. Wong, E. Pop, C. English, 2021, 2105.10791.

Low-Temperature Side Contact to Carbon Nanotube Transistors: Resistance Distributions Down to 10 nm Contact Length.

H. Wong, S. Mitra, J. Bokor, 2019, Nano letters.

Technology Assessment Methodology for Complementary Logic Applications Based on Energy–Delay Optimization

Lan Wei, H.-S Philip Wong, Saeroonter Oh, 2011, IEEE Transactions on Electron Devices.

Thermal conductivity measurement of amorphous dielectric multilayers for phase-change memory power reduction

Kenneth E. Goodson, Mehdi Asheghi, Scott W. Fong, 2016 .

Thermoelectric Characterization and Power Generation Using a Silicon-on-Insulator Substrate

M. Asheghi, Jaeho Lee, SangBum Kim, 2012, Journal of Microelectromechanical Systems.

Temperature-dependent studies of the electrical properties and the conduction mechanism of HfOx-based RRAM

Tayfun Gokmen, Seyoung Kim, H. Wong, 2014, Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Metal/III-V effective barrier height tuning using atomic layer deposition of high-κ/high-κ bilayer interfaces

K. Saraswat, H. Wong, Jenny Hu, 2011 .

Scanning microwave imaging of optically patterned Ge2Sb2Te5

H. Wong, H. Mabuchi, A. Sakdinawat, 2019, Applied Physics Letters.

Device study, chemical doping, and logic circuits based on transferred aligned single-walled carbon nanotubes

H.-S. Philip Wong, Subhasish Mitra, Albert Lin, 2008 .

The Effect of Donor/Acceptor Nature of Interface Traps on Ge MOSFET Characteristics

Duygu Kuzum, Tejas Krishnamohan, K. Saraswat, 2011, IEEE Transactions on Electron Devices.

Monolithic three-dimensional integration of carbon nanotube FET complementary logic circuits

Hai Wei, Subhasish Mitra, H.-S Philip Wong, 2013, 2013 IEEE International Electron Devices Meeting.

Compact models of emerging devices

H-S Philip Wong, Lan Wei, Ximeng Guan, 2013, 2013 IEEE International Conference of Electron Devices and Solid-state Circuits.

Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection

Hai Wei, Jie Zhang, H.-S. Philip Wong, 2011, 2011 International Electron Devices Meeting.

32-bit Processor core at 5-nm technology: Analysis of transistor and interconnect impact on VLSI system performance

Saurabh Sinha, H.-S. Philip Wong, Brian Cline, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage

H.-S. Philip Wong, Subhasish Mitra, Roger T. Howe, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Energy-Reversible Complementary NEM Logic Gates

D. Elata, K. Akarvardar, R. Howe, 2008, 2008 Device Research Conference.

Low temperature (≤ 380°C) and high performance Ge CMOS technology with novel source/drain by metal-induced dopants activation and high-k/metal gate stack for monolithic 3D integration

P. Kapur, M. Tada, Hyun-Yong Yu, 2008, 2008 IEEE International Electron Devices Meeting.

A Compact Model for Metal–Oxide Resistive Random Access Memory With Experiment Verification

Shimeng Yu, Lin Yang, Zizhen Jiang, 2016, IEEE Transactions on Electron Devices.

Compact Modeling of Conducting-Bridge Random-Access Memory (CBRAM)

Shimeng Yu, H.-S Philip Wong, Shimeng Yu, 2011, IEEE Transactions on Electron Devices.

Sub-0.5 nm Interfacial Dielectric Enables Superior Electrostatics: 65 mV/dec Top-Gated Carbon Nanotube FETs at 15 nm Gate Length

H. Wong, S. Mitra, G. Pitner, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Technology Projection Using Simple Compact Models

H.-S. Philip Wong, Jie Deng, Lan Wei, 2009, 2009 International Conference on Simulation of Semiconductor Processes and Devices.

Threshold Voltage and On–Off Ratio Tuning for Multiple-Tube Carbon Nanotube FETs

S. Mitra, N. Patil, H. Wong, 2009, IEEE Transactions on Nanotechnology.

Carrier density and quantum capacitance for semiconducting carbon nanotubes

H.-S. Philip Wong, Deji Akinwande, Jiale Liang, 2008 .

Study of DSA interaction range using Gaussian convolution

Germain Fenger, Hon-Sum Philip Wong, Joost Bekaert, 2015, Advanced Lithography.

CeO2 Doping of Hf0.5Zr0.5O2 Thin Films for High Endurance Ferroelectric Memories

H. Wong, Aranyak Mehta, P. McIntyre, 2022, Advanced Electronic Materials.

Band to Band Tunneling Study in High Mobility Materials : III-V, Si, Ge and strained SiGe

K. Saraswat, H. Wong, T. Krishnamohan, 2007, 2007 65th Annual Device Research Conference.

Ultralow–switching current density multilevel phase-change memory on a flexible substrate

Asir Intisar Khan, H. Wong, E. Pop, 2021, Science.

Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mispositioned Carbon Nanotubes

Hai Wei, J. Zhang, S. Mitra, 2011, IEEE Transactions on Nanotechnology.

Monolithic three-dimensional integrated circuits using carbon nanotube FETs and interconnects

Hai Wei, H.-S. Philip Wong, Subhasish Mitra, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Gate Quantum Capacitance Effects in Nanoscale Transistors.

H. Wong, A. Javey, G. Pitner, 2019, Nano letters.

Hysteresis-Free Carbon Nanotube Field-Effect Transistors.

H.-S. Philip Wong, Subhasish Mitra, Gage Hills, 2017, ACS nano.

Spectroscopic Evidence for Exceptional Thermal Contribution to Electron Beam-Induced Fragmentation

D. F. Ogletree, H. Wong, D. Milliron, 2010 .

Analytical Model of Carbon Nanotube Electrostatics: Density of States, Effective Mass, Carrier Density, and Quantum Capacitance

H. Wong, Y. Nishi, D. Akinwande, 2007, 2007 IEEE International Electron Devices Meeting.

TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits

H.-S. Philip Wong, Subhasish Mitra, S. Simon Wong, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Carbon nanotube field effect transistors - fabrication, device physics, and circuit implications

R. Martel, V. Derycke, H. Wong, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

Carbon nanotube circuits: Living with imperfections and variations

H.-S. Philip Wong, Nishant Patil, Subhasish Mitra, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits

H.-S. Philip Wong, Jie Deng, Nishant Patil, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

In-Situ Grown Graphene Enabled Copper Interconnects With Improved Electromigration Reliability

H. Wong, Zhongwei Zhu, Ling Li, 2019, IEEE Electron Device Letters.

BEOL compatible graphene/Cu with improved electromigration lifetime for future interconnects

Tao Wang, H.-S. Philip Wong, Alex Yoon, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Device and circuit optimization of RRAM for neuromorphic computing

H.-S. Philip Wong, Wenqiang Zhang, Dong Wu, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Challenges and opportunities toward online training acceleration using RRAM-based hardware neural network

H.-S. Philip Wong, Chih-Cheng Chang, Tuo-Hung Hou, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Understanding metal oxide RRAM current overshoot and reliability using Kinetic Monte Carlo simulation

Shimeng Yu, Ximeng Guan, Shimeng Yu, 2012, 2012 International Electron Devices Meeting.

Beyond-CMOS Technologies for Next Generation Computer Design

Rasit O. Topaloglu, H.-S. Philip Wong, H. Wong, 2018 .

Impact of III–V and Ge Devices on Circuit Performance

H.-S. Philip Wong, Soyoung Kim, S. Simon Wong, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Technology and device scaling considerations for CMOS imagers

Hon-Sum Philip Wong, H. Wong, 1996 .

Design strategy for integrating DSA via patterning in sub-7 nm interconnects

Geert Vandenberghe, H.-S. Philip Wong, Wim Dehaene, 2016, SPIE Advanced Lithography.

Ultrafast terahertz-induced response of GeSbTe phase-change materials

H. Wong, F. Xiong, E. Pop, 2014 .

Low-voltage high-performance flexible digital and analog circuits based on ultrahigh-purity semiconducting carbon nanotubes

Kwang-Ting Cheng, H.-S. Philip Wong, Tsung-Ching Huang, 2019, Nature Communications.

Crystallization properties and their drift dependence in phase-change memory studied with a micro-thermal stage

H.-S. Philip Wong, Byoungil Lee, Kenneth E. Goodson, 2011 .

Resistance and Threshold Switching Voltage Drift Behavior in Phase-Change Memory and Their Temperature Dependence at Microsecond Time Scales Studied Using a Micro-Thermal Stage

Byoungil Lee, Mehdi Asheghi, Fred Hurkx, 2011, IEEE Transactions on Electron Devices.

Thermal disturbance and its impact on reliability of phase-change memory studied by the micro-thermal stage

H.-S. Philip Wong, Byoungil Lee, Mehdi Asheghi, 2010, 2010 IEEE International Reliability Physics Symposium.

Artificial optic-neural synapse for colored and color-mixed pattern recognition

H-S Philip Wong, Duygu Kuzum, Jae-Woong Choi, 2018, Nature Communications.

Nanoscale CMOS - Proceedings of the IEEE

H. Wong, D. Frank, P. Solomon, 1999 .

Engineering thermal and electrical interface properties of phase change memory with monolayer MoS2

H. Wong, E. Pop, E. Yalon, 2019, Applied Physics Letters.

Reliability of graphene interconnects and n-type doping of carbon nanotube transistors

H. Wong, S. Mitra, Hong-Yu Chen, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

High-speed graphene interconnects monolithically integrated with CMOS ring oscillators operating at 1.3GHz

Jing Kong, H.-S. Philip Wong, Shinobu Fujita, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

14.3 A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques

H.-S. Philip Wong, Edith Beigné, Pascal Vivet, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell

H.-S. Philip Wong, Edith Beigne, Elisa Vianello, 2019, IEEE Transactions on Electron Devices.

First Demonstration of AC Gain From a Single-walled Carbon Nanotube Common-Source Amplifier

H.-S. Philip Wong, Jie Deng, Islamshah Amlani, 2006, 2006 International Electron Devices Meeting.

Frequency response of top-gated carbon nanotube field-effect transistors

D. Neumayer, A. Grill, J. Appenzeller, 2004, IEEE Transactions on Nanotechnology.

Sub-200 Ω·µm Alloyed Contacts to Synthetic Monolayer MoS2

K. Saraswat, H. Wong, E. Pop, 2021, International Electron Devices Meeting.

Monolithic 3D integration: A path from concept to reality

Hai Wei, H.-S. Philip Wong, Mohamed M. Sabry, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Neuromorphic architectures with electronic synapses

Gert Cauwenberghs, H.-S. Philip Wong, Weier Wan, 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).

Cross-Point Memory Array Without Cell Selectors—Device Characteristics and Data Storage Pattern Dependencies

Jiale Liang, H.-S Philip Wong, H. Wong, 2010, IEEE Transactions on Electron Devices.

High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning

H.-S.P. Wong, W. Wan, T. F. Wu, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Monolithic 3-D Integration

H.-S. Philip Wong, Subhasish Mitra, Max M. Shulaker, 2019, IEEE Micro.

Device and system level design considerations for analog-non-volatile-memory based neuromorphic architectures

Shimeng Yu, H.-S. Philip Wong, Sukru Burc Eryilmaz, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Ultra-low power Al2O3-based RRAM with 1μA reset current

H.-S. Philip Wong, Byoungil Lee, H. Wong, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

3D RRAM: Design and optimization

Jinfeng Kang, X. Y. Liu, P. Huang, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Cost-effective, transfer-free, flexible resistive random access memory using laser-scribed reduced graphene oxide patterning technology.

H. Wong, Yezhou Yang, T. Ren, 2014, Nano letters.

Beyond the Conventional MOSFET

H.-S. Philip Wong, H. Wong, 2001 .

Energy efficient programming of nanoelectronic synaptic devices for large-scale implementation of associative and temporal sequence learning

H.-S. Philip Wong, Duygu Kuzum, Rakesh G. D. Jeyasingh, 2011, 2011 International Electron Devices Meeting.

Design strategy for layout of Sub-Resolution Directed Self-Assembly Assist Features (SDRAFs)

H.-S. Philip Wong, Julien Ryckaert, Jan Doise, 2016 .

3-D Resistive Memory Arrays: From Intrinsic Switching Behaviors to Optimization Guidelines

Shimeng Yu, Peng Huang, Jinfeng Kang, 2015, IEEE Transactions on Electron Devices.

Wafer-scale fabrication and characterization of thin-film transistors with polythiophene-sorted semiconducting carbon nanotube networks.

H. Wong, S. Mitra, Zhenan Bao, 2012, ACS nano.

Ultra-low-energy three-dimensional oxide-based electronic synapses for implementation of robust high-accuracy neuromorphic computation systems.

Shimeng Yu, H. Wong, Lifeng Liu, 2014, ACS nano.

Device and Technology Challenges for Nanoscale CMOS

H.-S. Philip Wong, H. Wong, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Analysis of Temperature in Phase Change Memory Scaling

H. Wong, H.-S.P. Wong, S. Kim, 2007, IEEE Electron Device Letters.

Physical Layout Design of Directed Self-Assembly Guiding Alphabet for IC Contact Hole/via Patterning

H.-S. Philip Wong, He Yi, Kye Okabe, 2015, ISPD.

Contact pitch and location prediction for Directed Self-Assembly template verification

Yuelin Du, H.-S. Philip Wong, Zigang Xiao, 2015, The 20th Asia and South Pacific Design Automation Conference.

DSA template optimization for contact layer in 1D standard cell design

Yuelin Du, H.-S. Philip Wong, Zigang Xiao, 2014, Advanced Lithography.

DSA-aware detailed routing for via layer optimization

Yuelin Du, H.-S. Philip Wong, Zigang Xiao, 2014, Advanced Lithography.

Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library

Yuelin Du, H.-S. Philip Wong, He Yi, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Directed self-assembly guiding template design for contact hole patterning

H.-S.P. Wong, H. Yi, H. Wong, 2015 .

NEM relays using 2-dimensional nanomaterials for low energy contacts

H. Wong, Seunghyun Lee, A. Tang, 2013, 2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S).

NiO resistance change memory with a novel structure for 3D integration and improved confinement of conduction path

Byoungil Lee, H. Wong, Byoungil Lee, 2006, 2009 Symposium on VLSI Technology.

Recent progress of resistive switching random access memory (RRAM)

Shimeng Yu, Ximeng Guan, H. P. Wong, 2012, 2012 IEEE Silicon Nanoelectronics Workshop (SNW).

Recent progress of phase change memory (PCM) and resistive switching random access memory (RRAM)

Shimeng Yu, H.-S. Philip Wong, Byoungil Lee, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture

Shimeng Yu, Bing Chen, H.-S. Philip Wong, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Carbon Nanotube Quantum Capacitance for Nonlinear Terahertz Circuits

H. Wong, Y. Nishi, D. Akinwande, 2009, IEEE Transactions on Nanotechnology.

Next-Generation Ultrahigh-Density 3-D Vertical Resistive Switching Memory (VRSM)—Part II: Design Guidelines for Device, Array, and Architecture

Shosuke Fujii, Haitong Li, H.-S. Philip Wong, 2019, IEEE Transactions on Electron Devices.

Design considerations of synaptic device for neuromorphic computing

Shimeng Yu, H.-S. Philip Wong, Duygu Kuzum, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Compact modeling and design optimization of carbon nanotube field-effect transistors for the sub-10-nm technology nodes

H. Wong, E. Pop, Chi-Shuen Lee, 2015, 2015 73rd Annual Device Research Conference (DRC).

Contact-hole patterning for random logic circuits using block copolymer directed self-assembly

H.-S. Philip Wong, Jie Zhang, He Yi, 2012, Advanced Lithography.

Computational simulation of block copolymer directed self-assembly in small topographical guiding templates

H.-S. Philip Wong, He Yi, Azat Latypov, 2013, Advanced Lithography.

Surface Science of Catalyst Dynamics for Aligned Carbon Nanotube Synthesis on a Full-Scale Quartz Wafer

H. Wong, Y. Nishi, D. Akinwande, 2009 .

1D thickness scaling study of phase change material (Ge2Sb2Te5) using a pseudo 3-terminal device

H.-S. Philip Wong, Joo-Tae Moon, Yuan Zhang, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

High performance double-gate device technology challenges and opportunities

Edward J. Nowak, Meikei Leong, H.-S. Philip Wong, 2002, Proceedings International Symposium on Quality Electronic Design.