S. Muroga

发表

S. Muroga, I. Toda, S. Takasu, 1961 .

Saburo Muroga, S. Muroga, 1971 .

On the Capacity of a Discrete Channel. I Mathematical expression of capacity of a channel which is disturbed by noise in its every one symbol and expressible in one state diagram

S. Muroga, 1953 .

Majority Decision Functions of up to Six Variables

S. Muroga, I. Toda, M. Kondo, 1962 .

Advances in Information Systems Science

M. Harrison, S. Muroga, R. Shumaker, 1981, Springer US.

Comments on"Generalization ofConsensus Theory and Application totheMinimization ofBoolean Functions"

S. Muroga, 1979 .

Binary Decision Diagrams

Saburo Muroga, Shin-ichi Minato, S. Muroga, 2000, The VLSI Handbook.

Enumerationof Threshold Functions

S. Muroga, 1970 .

Adaptive linear classifier by linear programming, by Toshihide Ibaraki and Saburo Muroga

S. Muroga, T. Lbaraki, 2020 .

Table 1: Redesign 5 Implementation and Results Figure 4: Multi-level Logic Minimization 3.2 Multi-level Logic Minimization 4 Logic Synthesis from the Results of Boolean Unication

J. N. Culliney, A. Sangiovanni-Vincentelli, G. Hachtel, 1991 .

The principle of majority decision logical elements and the complexity of their circuits

Saburo Muroga, S. Muroga, 1959, IFIP Congress.

Logic Synthesis with a Minimum Number of Negative Gates

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Logic Synthesis with NAND (or NOR) Gates in Multi-levels

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Logic Synthesizer with Optimizations in Two Phases

Saburo Muroga, Ko Yoshikawa, S. Muroga, 2000, The VLSI Handbook.

Mask-Programmable Gate Arrays

Saburo Muroga, S. Muroga, 1999, The VLSI Handbook.

VLSI system design

Saburo Muroga, S. Muroga, 1982 .

Minimum Parallel Binary Adders with NOR (NAND) Gates

Hung Chi Lai, Saburo Muroga, S. Muroga, 1979, IEEE Transactions on Computers.

Sequential networks

Saburo Muroga, S. Muroga, 2000 .

Pass Transistors

Saburo Muroga, Kazuo Yano, S. Muroga, 2000, The VLSI Handbook.

Gate arrays

Saburo Muroga, S. Muroga, 2000 .

Logic Properties of Transistor Circuits

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Logic Synthesis with AND and OR Gates in Two Levels

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Logic design and switching theory

Saburo Muroga, S. Muroga, 1979 .

Binary Decision Diagrams

Saburo Muroga, Shi-ichi Minato, S. Muroga, 2000, The VLSI Handbook.

Emitter-Coupled Logic

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Logic Synthesis with AND and OR Gates in Multi-levels

Saburo Muroga, Yuichi Nakamura, S. Muroga, 2000, The VLSI Handbook.

Full-Custom and Semi-Custom Design

Saburo Muroga, S. Muroga, 1999, The VLSI Handbook.

Sequential Networks with AND and OR Gates

Saburo Muroga, S. Muroga, 1999, The VLSI Handbook.

Logic Synthesis AND and OR Gates in Two Levels

Saburo Muroga, S. Muroga, 2003 .

Simplification of Logic Expressions

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Cell-Library Design Approach

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Field-Programmable Gate Arrays

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Programmable Logic Devices

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Basic Theory of Logic Functions

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Ultra Large-Scale Integration Design

Saburo Muroga, S. Muroga, 2003 .

Logic Synthesizer by the Transduction Method

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Expressions of Logic Functions

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

On the capacity of a noisy continuous channel

Saburo Muroga, S. Muroga, 1957, IRE Trans. Inf. Theory.

Computer-Aided Logic Synthesis for VLSI Chips

Saburo Muroga, S. Muroga, 1991, Adv. Comput..

The Transduction Method-Design of Logic Networks Based on Permissible Functions

Yahiko Kambayashi, Hung Chi Lai, Saburo Muroga, 1989, IEEE Trans. Computers.

Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables

Hung Chi Lai, Saburo Muroga, S. Muroga, 1987, IEEE Transactions on Computers.

Properties of Wired Logic

Yahiko Kambayashi, Saburo Muroga, S. Muroga, 1986, IEEE Transactions on Computers.

Automated Logic Design of Mos Networks

Hung Chi Lai, Saburo Muroga, S. Muroga, 1985 .

Minimization of Logic Networks Under a Generalized Cost Function

Hung Chi Lai, Saburo Muroga, S. Muroga, 1976, IEEE Transactions on Computers.

Optimal One-Bit Full Adders With Different Types of Gates

Saburo Muroga, Tso-Kai Liu, Keith R. Hohulin, 1974, IEEE Transactions on Computers.

Enumeration of Threshold Functions of Eight Variables

Saburo Muroga, Charles R. Baugh, Teiichi Tsuboi, 1970, IEEE Transactions on Computers.

Absolute Minimization of Completely Specified Switching Functions

Saburo Muroga, Sung Je Hong, S. Muroga, 1991, IEEE Trans. Computers.

Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions

Tomoyasu Nakagawa, Saburo Muroga, Ming Huei Young, 1979, IEEE Transactions on Computers.

Lower Bounds of the Number of Threshold Functions and a Maximum Weight

Saburo Muroga, S. Muroga, 1962, IEEE Trans. Electron. Comput..

Functional forms of majority functions and a necessary and sufficient condition for their realizability

Saburo Muroga, S. Muroga, 1961, SWCT.

Timing optimization for multi-level combinational networks

Saburo Muroga, Kuang-Chien Chen, S. Muroga, 1990, DAC '90.